Flip chip interconnection pad layout
View Patent ↗A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.
1. A semiconductor chip, having a die pad layout for flip chip interconnect having signal pads disposed primarily in a perimeter region near an edge of the die, and having power/ground pads disposed primarily in an inboard region, wherein fewer than 10% of the power/ground pads are located within the perimeter region, and wherein fewer than 10% of the signal pads are located within the inboard region.
2. The semiconductor chip of claim 1 wherein the perimeter region consists essentially of a peripheral row generally parallel to a die edge.
3. The semiconductor chip of claim 1 wherein the perimeter region consists essentially of a peripheral array, generally parallel to a die edge.
4. The semiconductor chip of claim 3 signal pads are arranged primarily in at least two rows parallel to a die edge.
5. The semiconductor chip of claim 4 wherein the signal pads in adjacent rows are in a staggered arrangement.
6. The semiconductor chip of claim 4 wherein the signal pads in adjacent rows are in an orthogonal arrangement.
7. The semiconductor chip of claim 1 wherein the inboard region consists essentially of an array near the center of the die.
8. The semiconductor chip of claim 7 wherein the inboard region consists essentially of a rectangular array near the center of the die.
9. The semiconductor chip of claim 7 wherein a central area of the die has no pads.
10. The semiconductor chip of claim 9 wherein the power/ground pads are primarily arranged in at least two rows parallel to a die edge inboard from and near the signal pads.
11. The semiconductor chip of claim 1 wherein fewer than 5% of the power/ground pads are located within the perimeter region.
12. The semiconductor chip of claim 1 wherein fewer than 2% of the power/ground pads are located within the perimeter region.
13. The semiconductor chip of claim 1 wherein none of the power/ground pads is located within the perimeter region.
14. The semiconductor chip of claim 1 wherein fewer than 5% of the signal pads are located within the inboard region.
15. The semiconductor chip of claim 1 wherein fewer than 2% of the signal pads are located within the inboard region.
16. The semiconductor chip of claim 1 wherein none of the signal pads is located within the inboard region.