Semiconductor package having double layer leadframe
View Patent ↗A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along an edge of the package, and in some embodiments in a row along each of the four edges of the package. The leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other; in a plan view, the leads of the first leadframe appear to be interdigitated with the leads of the second leadframe.
1. A leadframe package comprising a double leadframe assembly wherein a first lead frame has a central die paddle and peripheral leads outside the outer perimeter of and coplanar with the central die paddle having input/output contact portions of the first leadframe exposed in a row of first contacts at an edge and a bottom of the package and wherein a second lead frame has peripheral leads outside the outer perimeter of the central die paddle having bottom surfaces being coplanar with that of the central die paddle and input/output contact portions of the second leadframe exposed at a bottom of the package in a row of second contacts inboard from the row of first contacts.
2. The package of claim 1 wherein the double leadframe assembly comprises the second leadframe, superimposed over the first leadframe in the package, having the peripheral leads.
3. The package of claim 2 wherein the peripheral leads of the leadframes are situated in at least one row along an edge of the package.
4. The package of claim 3 wherein the peripheral leads of the leadframes are situated in a row along each of the four edges of the package.
5. The package of claim 2 wherein the leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other.
6. The package of claim 5 wherein in a plan view the leads of the first leadframe are interdigitated with the leads of the second leadframe.
7. The package of claim 2 wherein contacts in the row of second contacts are staggered in relation to contacts in the row of first contacts.
8. The package of claim 2 wherein the input/output contact portions of the first leadframe are exposed in a row of first contacts at the edge of the package.
9. An electronic device comprising the package of claim 1 .