Patent Assignment
Reel/Frame 064803/0109
Corrective Assignment to Correct the Correct the Spelling of Assignee's Name from "Stats Chippac Pte. Lte," to "Stats Chippac Pte. Ltd." Previously Recorded at Reel: 038401 Frame: 0532. Assignor(S) Hereby Confirms the Assignment.
Recorded: 2023-09-01
Pages: 19
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SINGAPORE
Covered Properties
(66)
Chip Scale Package with Flip Chip Interconnect
Integrated Circuit Leadframe and Fabrication Method Therefor
Integrated Circuit Package System with Multi-Surface Die Attach Pad
Embedded Integrated Circuit Package-on-Package System
Integrated Circuit Package System with Bonding in Via
Method for Making a Semiconductor Multi-Package Module Having Inverted Wire Bond Carrier Second Package
Mountable Integrated Circuit Package System with Mountable Integrated Circuit Die
Integrated Circuit Package System with Lead-Frame Paddle Scheme for Single Axis Partial Saw Isolation
Planar Encapsulation and Mold Cavity Package in Package System
Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonator
Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection
Integrated Circuit Packaging System with Multi-Stacked Flip Chips and Method of Manufacture Thereof
Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier
Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die
Integrated Circuit Packaging System with Cap Layer and Method of Manufacture Thereof
Miniaturized Wide-Band Baluns for Rf Applications
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die Tsv
Semiconductor Device and Method of Forming Bump Structure with Multi-Layer Ubm Around Bump Formation Area
Integrated Circuit Packaging System with Stackable Package and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
Integrated Circuit Packaging System with via and Method of Manufacture Thereof
Integrated Circuit Packaging System with Encapsulation and Method of Manufacture Thereof
Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps
Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape
Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
Integrated Circuit Package System with Package Stacking and Method of Manufacture Thereof
Integrated Circuit Packaging System with Trenches and Method of Manufacture Thereof
Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices
Integrated Circuit Packaging System with Lead Encapsulation and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure
Semiconductor Device and Method of Forming Bump-on-Lead Interconnection
Integrated Circuit Packaging System with Dielectric Support and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive Tov in Peripheral Area Around Semiconductor Die
Integrated Circuit Package-on-Package System with Underfilling Structures and Method of Manufacture Thereof
Integrated Circuit Packaging System with Collapsed Multi-Integration Package and Method of Manufacture Thereof
Integrated Circuit Packaging System with Interconnects and Method of Manufacture Thereof
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Integrated Circuit Packaging System with Package on Package Support and Method of Manufacture Thereof
Integrated Circuit Package System with Contoured Encapsulation and Method for Manufacturing Thereof
Semiconductor System with Fine Pitch Lead Fingers and Method of Manufacturing Thereof
Integrated Circuit Packaging System with Embedded Thermal Heat Shield and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces
Semiconductor Device and Method of Forming Guard Ring Around Conductive Tsv Through Semiconductor Wafer
Integrated Circuit Packaging System with Interposer Interconnections and Method of Manufacture Thereof
Integrated Circuit Packaging System with Interconnects and Method of Manufacture Thereof
Integrated Circuit Packaging System with Leads and Method of Manufacture Thereof
Integrated Circuit Packaging System with Film Assistance Mold and Method of Manufacture Thereof
Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
Semiconductor Device and Method of Forming Prefabricated Emi Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
Integrated Circuit Packaging System with Encapsulation and Leadframe Etching and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Stud Bumps Over Embedded Die
Dual Molded Multi-Chip Package System
Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die
Bump-On-Lead Flip Chip Interconnection
Integrated Circuit Package System with Stackable Devices and a Method of Manufacture Thereof
Apparatus for Thermally Enhanced Semiconductor Package
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
Integrated Circuit Packaging System with Shielding Spacer and Method of Manufacture Thereof
Patent:
8,569,870 →
Application:
13/531,941 →
Solder Joint Flip Chip Interconnection Having Relief Structure
Patent:
44,562 →
Application:
13/558,953 →
Semiconductor Device Including Bump Formed on Substrate to Prevent Extrimely-Low Dielectric Constant (Elk) Interlayer Dielectric Layer (Ild) Delamination During Reflow Process
Semiconductor Device and Method of Forming Air Gap Adjacent to Stress Sensitive Region of the Die
Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection
Patent:
44,500 →
Application:
13/752,157 →
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
Patent:
44,579 →
Application:
13/756,679 →
Bump-On-Lead Flip Chip Interconnection
Patent:
44,524 →
Application:
13/756,779 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Merger and Change of Name
Aug 6, 2015
From: CHIPPAC, INC.; STATS CHIPPAC, INC.
To: STATS CHIPPAC, INC.
Reel/Frame 036286/0612 →
Change of Name
Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0343 →
Change of Name
Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
Release of Security Interest
Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
Assignment of Assignor's Interest
Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
Release of Security Interest
Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
Release of Security Interest
Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
Assignment of Assignor's Interest
Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →