Integrated circuit packaging system with multi-stacked flip chips and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

depositing a through-conductor on the base substrate;

depositing an epitaxial layer on the base substrate and around the through-conductor;

implanting a doped epitaxial layer into the epitaxial layer;

forming a metal trace connected to the through-conductor;

depositing a dielectric surrounding the metal trace, the through-conductor extending into the dielectric; and

removing the base substrate.

2. The method as claimed in claim 1 further comprising:

implanting a transistor well into the doped epitaxial layer.

3. The method as claimed in claim 1 further comprising:

depositing an interconnect connected to the metal trace.

4. The method as claimed in claim 1 further comprising:

planarizing the through-conductor to make a bottom surface of the through-conductor level with a bottom of the epitaxial layer.

5. The method as claimed in claim 1 wherein:

depositing the dielectric includes depositing the dielectric around a bottom portion of the through-conductor that extends below a bottom of the epitaxial layer.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

depositing a through-conductor on the base substrate;

depositing an epitaxial layer on the base substrate and around the through-conductor;

implanting a doped epitaxial layer into the epitaxial layer;

forming a metal trace connected to the through-conductor;

depositing a dielectric surrounding the metal trace, the through-conductor extending into the dielectric;

removing the base substrate;

mounting a substrate below the metal trace; and

connecting the substrate to the metal trace with an interconnect.

7. The method as claimed in claim 6 wherein:

providing the base substrate includes providing a silicon mono-crystalline wafer; and

implanting the doped epitaxial layer includes doping with Diborane, Phosphine, Arsine, or a combination thereof.

8. The method as claimed in claim 6 wherein:

providing the through-conductor includes providing a through-conductor terminating in a through-conductor pad near a top of the epitaxial layer; and

further comprising:

encapsulating the metal trace, the dielectric, but not the through-conductor pad with an encapsulation.

9. The method as claimed in claim 6 wherein:

providing the through-conductor, depositing the epitaxial layer, forming the metal trace, and depositing the dielectric includes providing a through-conductor,

depositing a epitaxial layer, forming a metal trace, and depositing a dielectric to form a first flip chip; and

further comprising:

mounting a second flip chip above the first flip chip;

connecting the second flip chip to the through-conductor of the first flip chip with the interconnects;

reflowing the interconnects prior to or after mounting the second flip chip; and

encapsulating the first flip chip and the second flip chip with an encapsulation, filling between the first flip chip and the substrate with an underfill, or a combination thereof.

10. The method as claimed in claim 6 further comprising:

mounting external interconnects below the substrate.

11. An integrated circuit packaging system comprising:

an epitaxial layer;

a doped epitaxial layer implanted into the epitaxial layer;

a through-conductor through the epitaxial layer;

a metal trace connected to the through-conductor; and

a dielectric that surrounds the metal trace, the through-conductor extending into the dielectric.

12. The system as claimed in claim 11 wherein:

the doped epitaxial layer includes a transistor well.

13. The system as claimed in claim 11 further comprising:

an interconnect connected to the metal trace.

14. The system as claimed in claim 11 further comprising:

a bottom surface of the through-conductor is level with a bottom of the epitaxial layer.

15. The system as claimed in claim 11 wherein:

the dielectric is deposited around a bottom portion of the through-conductor that extends below a bottom of the epitaxial layer.

16. The system as claimed in claim 11 further comprising:

a substrate mounted below the metal trace; and

the substrate connected to the metal trace with an interconnect.

17. The system as claimed in claim 16 wherein:

the doped epitaxial layer is doped with Diborane, Phosphine, Arsine, or a combination thereof.

18. The system as claimed in claim 16 further comprising:

a through-conductor pad near a top of the epitaxial layer; and

an encapsulation that encapsulates the metal trace, the dielectric, but not the through-conductor pad.

19. The system as claimed in claim 16 wherein:

the through-conductor, the epitaxial layer, the metal trace, and the dielectric form a first flip chip; and

further comprising:

a second flip chip mounted above the first flip chip; and

an encapsulation that encapsulates the first flip chip and the second flip chip, an underfill that fills between the first flip chip and the substrate, or a combination thereof.

20. The system as claimed in claim 16 further comprising:

external interconnects mounted below the substrate.