IP Library Granted Patent US 8,519,536
Granted Patent B2
US 8,519,536 · App. 13/691,427 · Granted Aug 27, 2013

Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process

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Quick Facts
Patent No.
US 8,519,536
App. No.
13/691,427
Granted
Aug 27, 2013
Kind
B2
Abstract

A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Claims (50)

1. A semiconductor device, comprising:

a substrate;

a first insulating layer formed over the substrate including an opening extending through the first insulating layer and into the substrate;

a first bump material disposed in the opening and electrically connected to the substrate; and

a semiconductor die disposed over the substrate and electrically connected to the first bump material.

2. The semiconductor device of claim 1 , further including:

a second insulating layer formed over the first insulating layer including an opening extending through the second insulating layer to the first bump material; and

a second bump material disposed within the opening in the second insulating layer over the first bump material.

3. The semiconductor device of claim 1 , further including a second bump material disposed over the first bump material.

4. The semiconductor device of claim 3 , wherein the first bump material includes a non-fusible material and the second bump material includes a fusible material.

5. The semiconductor device of claim 1 , wherein the first bump material includes a conductive pillar or stacked bumps.

6. The semiconductor device of claim 1 , further including:

a first conductive layer formed over a surface of the semiconductor die;

a second insulating layer formed over the first conductive layer and the surface of the semiconductor die; and

a second conductive layer formed over the first conductive layer and second insulating layer.

7. The semiconductor device of claim 1 , wherein the semiconductor die includes a flipchip type semiconductor die.

8. A semiconductor device, comprising:

a substrate;

a first insulating layer formed over the substrate including an opening extending through the first insulating layer and into the substrate;

an interconnect structure disposed in the opening and electrically connected to the substrate; and

a semiconductor die disposed over the substrate and electrically connected to the interconnect structure.

9. The semiconductor device of claim 8 , wherein the interconnect structure includes a non-fusible portion and fusible portion.

10. The semiconductor device of claim 8 , further including a bump material disposed over the interconnect structure.

11. The semiconductor device of claim 8 , wherein the interconnect structure includes a conductive pillar or stacked bumps.

12. The semiconductor device of claim 8 , further including:

a first conductive layer formed over a surface of the semiconductor die;

a second insulating layer formed over the first conductive layer and the surface of the semiconductor die; and

a second conductive layer formed over the first conductive layer and second insulating layer.

13. The semiconductor device of claim 8 , wherein the semiconductor die includes a flipchip type semiconductor die.

14. A semiconductor device, comprising:

a substrate;

an interconnect structure including a non-fusible portion extending into the substrate and fusible portion disposed over the non-fusible portion; and

a semiconductor die disposed over the substrate and electrically connected to the interconnect structure.

15. The semiconductor device of claim 14 , further including a first insulating layer formed over the substrate including an opening extending through the first insulating layer to the substrate, wherein the interconnect structure is disposed in the opening and electrically connected to the substrate.

16. The semiconductor device of claim 15 , further including a second insulating layer formed over the first insulating layer.

17. The semiconductor device of claim 14 , wherein the interconnect structure includes a conductive pillar or stacked bumps.

18. The semiconductor device of claim 14 , further including:

a first conductive layer formed over a surface of the semiconductor die;

a second insulating layer formed over the first conductive layer and the surface of the semiconductor die; and

a second conductive layer formed over the first conductive layer and second insulating layer.

19. The semiconductor device of claim 14 , wherein the semiconductor die includes a flipchip type semiconductor die.

20. A semiconductor device, comprising:

a substrate;

an interconnect structure disposed over the substrate including a portion extending into the substrate; and

a semiconductor die disposed over the substrate and electrically connected to the interconnect structure.

21. The semiconductor device of claim 20 , further including a first insulating layer formed over the substrate including an opening extending through the first insulating layer to the substrate, wherein the interconnect structure is disposed in the opening and electrically connected to the substrate.

22. The semiconductor device of claim 20 , wherein the interconnect structure includes a non-fusible portion and fusible portion.

23. The semiconductor device of claim 20 , further including a bump material disposed over the interconnect structure.

24. The semiconductor device of claim 20 , wherein the interconnect structure includes a conductive pillar or stacked bumps.

25. The semiconductor device of claim 20 , wherein the semiconductor die includes a flipchip type semiconductor die.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0360 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →