Dual molded multi-chip package system

1. A method of manufacturing a dual molded multi-chip package system comprising;

forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto with a first active side of the first integrated circuit die exposed to the external environment,

forming a solder mask over the first encapsulation;

connecting a trace between and in direct contact with the lead and the first integrated circuit die;

connecting an external interconnect in direct contact with an end of the trace;

mounting a semiconductor device over the first encapsulation and connected to the lead; and

forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system, wherein forming the second encapsulation includes covering the lead and the first encapsulation coplanar with a first surface of the lead without covering the first active side.

2. The method as claimed in claim 1 wherein forming the solder mask includes forming the solder mask over the first active side.

3. The method as claimed in claim 1 wherein mounting the semiconductor device includes mounting a third integrated circuit die.

4. A dual molded multi-chip package system comprising:

an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead;

a semiconductor device over the first encapsulation;

an internal interconnect between the lead and the semiconductor device;

a trace between and in direct contact with the lead and the first integrated circuit die;

an external interconnect in direct contact with an end of the trace;

a second encapsulation over the semiconductor device and the embedded integrated circuit package system, wherein the embedded integrated circuit package system has the first encapsulation partially covering the first integrated circuit die and the lead connected thereto with a first active side of the first integrated circuit die exposed to the external environment;

the semiconductor device is attached to the first encapsulation with a first adhesive and connected to the lead;

the second encapsulation is over the semiconductor device and the embedded integrated circuit package system without covering the first active side, wherein the second encapsulation includes a cover for the lead and the first encapsulation coplanar with a first surface of the lead, and further comprising:

a solder mask over the first encapsulation.

5. The system as claimed in claim 4 further comprising an extension of the lead.

6. The system as claimed in claim 4 wherein the trace is between a bond site and the first integrated circuit die.

7. The system as claimed in claim 4 , wherein the trace is under the first encapsulation.

8. The system as claimed in claim 4 , wherein the semiconductor device is connected to the first integrated circuit die with the trace.

9. The system as claimed in claim 4 wherein the solder mask includes the solder mask over the first active side.

10. The system as claimed in claim 4 wherein the semiconductor device includes a third integrated circuit die.