Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
View Patent ↗A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of first semiconductor die with a stress sensitive region;
forming a masking layer over the stress sensitive region and terminating at a boundary of the stress sensitive region;
depositing an underfill material over the semiconductor wafer and extending to the masking layer at the boundary of the stress sensitive region, the masking layer preventing formation of the underfill material over the stress sensitive region;
removing the masking layer leaving a cavity in the underfill material terminating at the boundary of the stress sensitive region;
singulating the semiconductor wafer into the first semiconductor die;
providing a second semiconductor die including a plurality of bumps formed over a surface of the second semiconductor die; and
disposing the first semiconductor die over the second semiconductor die by pressing the bumps into the underfill material with the cavity separating the stress sensitive region and second semiconductor die.
2. The method of claim 1 , further including:
providing an interconnect structure; and
disposing the second semiconductor die over the interconnect structure.
3. The method of claim 2 , further including:
forming a bond wire between the second semiconductor die and interconnect structure; and
depositing an encapsulant over the first and second semiconductor die, interconnect structure, and bond wire.
4. The method of claim 1 , further including forming a plurality of conductive vias through the first semiconductor die.
5. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a stress sensitive region;
providing a second semiconductor die including a plurality of bumps formed over a surface of the second semiconductor die;
depositing an underfill material over the surface of the second semiconductor die and around the bumps with an opening in the underfill material; and
disposing the first semiconductor die over the second semiconductor die with the opening in the underfill material separating the stress sensitive region and second semiconductor die.
6. The method of claim 5 , further including:
providing an interconnect structure; and
disposing the second semiconductor die over the interconnect structure.
7. The method of claim 6 , further including:
forming a bond wire between the second semiconductor die and interconnect structure; and
depositing an encapsulant over the first and second semiconductor die, interconnect structure, and bond wire.
8. The method of claim 5 , further including forming a conductive via through the first semiconductor die or second semiconductor die.
9. The method of claim 5 , further including
providing an interconnect structure
under the second semiconductor die.
10. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a stress sensitive region;
providing a second semiconductor die including a plurality of bumps formed over a surface of the second semiconductor die;
forming an underfill material over the first semiconductor die including a cavity formed in the underfill material over the stress sensitive region; and
disposing the first semiconductor die over the second semiconductor die by pressing the bumps into the underfill material with the cavity separating the stress sensitive region and second semiconductor die.
11. The method of claim 10 , further including:
providing an interconnect structure; and
disposing the second semiconductor die over the interconnect structure.
12. The method of claim 11 , further including depositing an encapsulant over the first semiconductor die, second semiconductor die, and interconnect structure.
13. The method of claim 12 , further including forming a bond wire between the second semiconductor die and interconnect structure.
14. The method of claim 10 , further including forming a conductive via through the first semiconductor die.
15. The method of claim 10 , further including
providing an interconnect structure
under the second semiconductor die.
16. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a stress sensitive region;
providing a second semiconductor die including a plurality of bumps formed over a surface of the second semiconductor die;
forming an underfill material over the second semiconductor die including a cavity formed in the underfill material; and
disposing the first semiconductor die over the second semiconductor die with the stress sensitive region aligned to the cavity to separate the stress sensitive region and second semiconductor die.
17. The method of claim 16 , further including:
providing an interconnect structure; and
disposing the second semiconductor die over the interconnect structure.
18. The method of claim 17 , further including depositing an encapsulant over the first semiconductor die, second semiconductor die, and interconnect structure.
19. The method of claim 18 , further including forming a bond wire between the second semiconductor die and interconnect structure.
20. The method of claim 16 , further including forming a conductive via through the first semiconductor die.