IP Library Granted Patent US 8,558,366
Granted Patent B2
US 8,558,366 · App. 13/324,380 · Granted Oct 15, 2013

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

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Quick Facts
Patent No.
US 8,558,366
App. No.
13/324,380
Granted
Oct 15, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Claims (64)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit;

mounting a routing structure having a functional side above the integrated circuit;

mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure;

forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure;

mounting a first-external-package-component to the routing structure; and

forming a first-external-package-encapsulation covering the first-external-package-component and in direct contact with the routing structure.

2. The method as claimed in claim 1 further comprising:

mounting a substrate below the integrated circuit; and

connecting the integrated circuit to the substrate with internal interconnects.

3. The method as claimed in claim 1 further comprising:

mounting a substrate below the integrated circuit; and

connecting the routing structure to the substrate with z-interconnects.

4. The method as claimed in claim 1 further comprising:

connecting an external-package to the vertical interconnect.

5. The method as claimed in claim 1 wherein:

mounting the vertical interconnect includes mounting vertical interconnects in two rows.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit;

mounting a routing structure having a functional side above the integrated circuit;

mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure;

forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure;

forming mold risers in the encapsulation with the mold risers rise vertically away from the routing structure;

connecting an external-package to the surface exposed from the encapsulation between the mold risers;

mounting a first-external-package-component to the routing structure; and

forming a first-external-package-encapsulation covering the first-external-package-component and in direct contact with the routing structure.

7. The method as claimed in claim 6 wherein:

mounting the integrated circuit includes mounting a wire-bonded die, a flip-chip, or a combination thereof; and

connecting the external-package to the surface exposed from the encapsulation includes connecting a flip-chip, an integrated circuit component package, or a combination thereof.

8. The method as claimed in claim 6 wherein:

forming the mold risers includes forming mold risers sufficiently high to provide structural support for the vertical interconnect and to provide a standoff height above the external package.

9. The method as claimed in claim 6 wherein:

forming the encapsulation covering the vertical interconnect includes forming the encapsulation around a vertical interconnect, forming a hole in the encapsulation and filling the hole with the vertical interconnect, or a combination thereof.

10. The method as claimed in claim 6 wherein:

mounting the vertical interconnect includes mounting the vertical interconnects along two edges of the routing structure.

11. An integrated circuit packaging system comprising:

an integrated circuit;

a routing structure having a functional side mounted above the integrated circuit;

a vertical interconnect mounted to the functional side of the routing structure and the vertical interconnect extends vertically away from the routing structure;

an encapsulation over the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and a surface of the routing structure remains exposed from the encapsulation, and a portion of the vertical interconnect remains exposed from the encapsulation above the surface of the routing structure;

a first-external-package-component mounted to the routing structure; and

a first-external-package-encapsulation covering the first-external-package-component and in direct contact with the routing structure.

12. The system as claimed in claim 11 further comprising:

a substrate below the integrated circuit; and

the integrated circuit is connected to the substrate with internal interconnects.

13. The system as claimed in claim 11 further comprising:

a substrate below the integrated circuit; and

the routing structure is connected to the substrate with z-interconnects.

14. The system as claimed in claim 11 further comprising:

an external-package connected to the vertical interconnect.

15. The system as claimed in claim 11 wherein:

the vertical interconnects are mounted in two rows.

16. The system as claimed in claim 11 further comprising:

mold risers formed in the encapsulation and rise vertically away from the routing structure; and

an external-package connected to the surface exposed from the encapsulation between the mold risers.

17. The system as claimed in claim 16 wherein:

the integrated circuit is a wire-bonded die, a flip-chip, or a combination thereof; and

the external-package is a flip-chip, an integrated circuit component package, or a combination thereof.

18. The system as claimed in claim 16 wherein:

the mold risers are sufficiently high to provide structural support for the vertical interconnect and to provide a standoff height above the external package.

19. The system as claimed in claim 16 wherein:

the vertical interconnect is an embedded-conductive-fillings formed in a hole of the encapsulation, an embedded solder ball or a combination thereof.

20. The system as claimed in claim 16 wherein:

the vertical interconnects are along two edges of the routing structure.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →