Integrated circuit package system with contoured encapsulation and method for manufacturing thereof
View Patent ↗A method for manufacturing an integrated circuit package system includes: providing a carrier; mounting an integrated circuit die on a top side of the carrier; connecting the integrated circuit die with the carrier; forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress; and forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect.
1. A method for manufacturing an integrated circuit package system comprising:
providing a carrier;
mounting an integrated circuit die on a flat top side of the carrier;
connecting the integrated circuit die with the carrier; and
forming an encapsulation, having a first region and a multi-sloped side as a contour, over the integrated circuit die, and wherein forming the encapsulation includes:
forming the first region having a first thickness and central to the encapsulation
forming the contour having a second region and a third region, the second region between and intersecting the first region and the third region, and
forming the contour having a second thickness at the intersection of the second region and the third region, the second thickness less than twenty percent the first thickness for reducing ejection stress damage.
2. The method as claimed in claim 1 wherein forming the encapsulation having the multi-sloped side includes forming an S-shaped side.
3. The method as claimed in claim 1 further comprising mounting a stacking integrated circuit package over the carrier and the encapsulation.
4. The method as claimed in claim 1 wherein:
connecting the integrated circuit die with the carrier includes:
connecting a bond wire between the integrated circuit die and the carrier; and forming the encapsulation having the multi-sloped side further includes:
forming the encapsulation to substantially conform to the bond wire.
5. A method of manufacturing an integrated circuit package system comprising:
providing a carrier;
mounting an integrated circuit die on a flat top side of the carrier;
connecting a bond wire between the integrated circuit die with the carrier; and
forming an encapsulation, having a first region and a multi-sloped side as a contour, over the integrated circuit die, and wherein forming the encapsulation includes:
forming the first region having a first thickness and central to the encapsulation,
forming the contour having a second region and a third region, the second region between and intersecting the first region and the third region, and
forming the contour having a second thickness at the intersection of the second region and the third region, the second thickness less than twenty percent the first thickness to substantially conform to the bond wire and for reducing ejection stress.
6. The method as claimed in claim 5 wherein forming the encapsulation includes:
forming a first region, as the central portion, having the first thickness that is horizontal and adjacent to the multi-sloped side; and
forming a second region, between the first region and a peripheral portion of the encapsulation having the second thickness.
7. The method as claimed in claim 5 wherein providing the carrier includes providing a substrate.
8. The method as claimed in claim 5 further comprising mounting a stacking integrated circuit package over the carrier and the encapsulation.
9. The method as claimed in claim 5 further comprising attaching an external interconnect with the carrier at an opposing side of the encapsulation.
10. An integrated circuit package system comprising:
a carrier;
an integrated circuit die on a flat top side of the carrier; and
an encapsulation, having a first region and a multi-sloped side as a contour, over the integrated circuit die, and wherein the encapsulation includes:
the first region having a first thickness and central to the encapsulation,
the contour having a second region and a third region, the second region between and intersecting the first region and the third region, and
the contour having a second thickness at the intersection of the second region and the third region, the second thickness less than twenty percent the first thickness for reducing ejection stress damage to the encapsulation.
11. The system as claimed in claim 10 wherein the encapsulation having the multi-sloped side includes an S-shaped side.
12. The system as claimed in claim 10 further comprising a stacking integrated circuit package over the carrier and the encapsulation.
13. The system as claimed in claim 10 further comprising a bond wire between the integrated circuit die and the carrier.
14. The system as claimed in claim 10 further comprising:
a bond wire between the integrated circuit die and the carrier; and wherein:
the encapsulation substantially conforms to the bond wire and the integrated circuit die.
15. The system as claimed in claim 14 wherein the encapsulation having the multi-sloped side includes:
a first region, as the central portion, having the first thickness that is horizontal and adjacent to the multi-sloped side; and
a second region, between the first region and a peripheral portion of the encapsulation having the second thickness.
16. The system as claimed in claim 14 wherein the carrier includes a substrate.
17. The system as claimed in claim 14 further comprising a stacking integrated circuit package over the carrier and the encapsulation.
18. The system as claimed in claim 14 further comprising an external interconnect attached with the carrier at an opposing side of the encapsulation.