IP Library Granted Patent US 9,000,579
Granted Patent B2
US 9,000,579 · App. 11/694,912 · Granted Apr 7, 2015

Integrated circuit package system with bonding in via

Inventors: Il Kwon Shim (Singapore, SG); Dario S. Filoteo, Jr. (Singapore, SG); Emmanuel Espiritu (Singapore, SG); Rachel Layda Abinan (Singapore, SG)
Assignee: STATS ChipPAC Ltd.
H01L23/49827H01L24/48H01L24/78H01L24/85H01L2224/48091H01L2224/48227H01L2224/48228H01L2224/48465H01L2224/48471H01L2224/48479H01L2224/4848H01L2224/49171H01L2224/73265H01L2224/78301H01L2224/85186H01L2924/01014H01L2924/014H01L2924/14H01L2924/30105H01L2924/30107H01L24/49H01L2924/01033H01L2224/32225H01L2924/10253
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Quick Facts
Patent No.
US 9,000,579
App. No.
11/694,912
Granted
Apr 7, 2015
Kind
B2
Abstract

An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.

Claims (60)

1. A method for manufacturing an integrated circuit package system comprising:

forming a substrate having a conductor and a substrate insulator between a first substrate layer and a second substrate layer, wherein the conductor includes:

a conductor base portion contacting a lower surface of the substrate insulator,

a conductor upper portion partially covered by the first substrate layer and configured to form a perimeter,

the conductor base portion partially covered by the second substrate layer, and

conductor intermediate portions extending and tapering from the conductor upper portion to an upper surface of the conductor base portion forming a plurality of contacting interfaces between the conductor intermediate portions and the u per surface of the conductor base portion, wherein the contacting interfaces collectively form an exposed area on the conductor base portion, wherein the exposed area is smaller than the perimeter;

attaching an integrated circuit die over the substrate;

attaching a die interconnect from the integrated circuit die to an exposed area of the conductor base portion; and

forming a substrate pad within the second substrate layer, the substrate pad below and contacting the conductor base portion opposite the exposed area thereof, an exposed bottom surface of the substrate pad is directly below the exposed area of the conductor base portion, the exposed bottom surface of the substrate pad is exposed from a substrate bottom surface providing electrical connectivity to a next level system.

2. The method as claimed in claim 1 wherein forming the substrate pad includes forming the substrate pad partially exposed from the second substrate layer.

3. The method as claimed in claim 1 wherein forming the substrate includes connecting a substrate connector to multiple layers of the substrate.

4. An integrated circuit package system comprising:

a substrate having a conductor and a substrate insulator between a first substrate layer and a second substrate layer, wherein the conductor includes:

a conductor base portion in contact with a lower surface of the substrate insulator,

a conductor upper portion partially covered by the first substrate layer and configured to form a perimeter,

the conductor base portion partially covered by the second substrate layer, and

conductor intermediate portions extending and from the conductor upper portion to an upper surface of the conductor base portion forming a plurality of contacting interfaces between the conductor intermediate portions and the upper surface of the conductor base portion, wherein the contacting interfaces collective form an exposed area on the conductor base, wherein the exposed area is smaller than the perimeter;

an integrated circuit die over the substrate;

a die interconnect attached from the integrated circuit die to an exposed area of the conductor base portion; and

a substrate pad within the second substrate layer, the substrate pad below and in contact with the conductor base portion opposite the exposed area thereof, an exposed bottom surface of the substrate pad is directly below the exposed area of the conductor base portion, the exposed bottom surface of the substrate pad is exposed from a substrate bottom surface providing electrical connectivity to a next level system.

5. The system as claimed in claim 4 wherein the substrate pad is partially exposed from the second substrate layer.

6. The system as claimed in claim 4 wherein the substrate includes a substrate connector is connected to multiple layers of the substrate.

7. The method as claimed in claim 1 wherein the conductor includes:

the conductor upper portion contacting a top surface of the substrate insulator,

the conductor base portion partially covered by the second substrate layer, and

the conductor intermediate portions contacting side surfaces of the substrate insulator connecting the conductor upper portion to the conductor base portion.

8. The method as claimed in claim 1 wherein attaching a die interconnect includes the die interconnect having stitch bonding or ball bonding entirely within the exposed area of the conductor base portion, and the die interconnect forming a connectivity end of the die interconnect entirely over and within the exposed area of the conductor base portion.

9. A method for manufacturing an integrated circuit package system comprising:

forming a substrate having a conductor and a substrate insulator between a first substrate layer and a second substrate layer, wherein the conductor includes:

a conductor upper portion contacting a top surface of the substrate insulator,

the conductor upper portion partially covered by the first substrate layer and configured to form a perimeter,

a conductor base portion partially covered by the second substrate layer,

conductor intermediate portions extending and tapering from the conductor upper portion to an upper surface of the conductor base portion forming a plurality of contacting interfaces between the conductor intermediate portions and the upper surface of the conductor base portion, wherein the contacting interfaces collectively form an exposed area on the conductor base portion, wherein the exposed area is small than the perimeter,

the conductor base portion contacting a lower surface of the substrate insulator, and

the conductor intermediate portions contacting side surfaces of the substrate insulator connecting the conductor upper portion to the conductor base portion;

attaching an integrated circuit die over the substrate;

attaching a die interconnect from the integrated circuit die to an exposed area of the conductor base portion; and

forming a substrate pad within the second substrate layer, the substrate pad below and contacting the conductor base portion opposite the exposed area thereof, an exposed bottom surface of the substrate pad is directly below the exposed area of the conductor base portion, the exposed bottom surface of the substrate pad is exposed from a substrate bottom surface providing electrical connectivity to a next level system.

10. The method as claimed in claim 9 wherein attaching a die interconnect includes the die interconnect having stitch bonding or ball bonding entirely within the exposed area of the conductor base portion, the die interconnect not contacting either the conductor intermediate portions or the conductor upper portion, and the die interconnect having a connectivity end of the die interconnect entirely over and within the exposed area of the conductor base portion.

11. The method as claimed in claim 9 wherein forming a substrate pad includes the substrate pad partially exposed from the second substrate layer leaving the exposed bottom surface of the substrate pad exposed from the second substrate layer, wherein the exposed bottom surface is within a recess of the second substrate layer and above a substrate bottom surface of the second substrate layer.

12. The method as claimed in claim 9 wherein forming the substrate includes connecting the conductor to a substrate connector connecting multiple layers of the substrate.

13. The system as claimed in claim 4 wherein the conductor includes:

the conductor upper portion in contact with a top surface of the substrate insulator,

the conductor base portion partially covered by the second substrate layer, and

the conductor intermediate portions in contact with side surfaces of the substrate insulator connected with the conductor upper portion and the conductor base portion.

14. The system as claimed in claim 4 wherein the die interconnect includes the die interconnect having stitch bonding or ball bonding entirely within the exposed area of the conductor base portion, and the die interconnect includes a connectivity end of the die interconnect entirely over and within the exposed area of the conductor base portion.

15. An integrated circuit package system comprising:

a substrate having a conductor and a substrate insulator between a first substrate layer and a second substrate layer, wherein the conductor includes:

a conductor upper portion in contact with a top surface of the substrate insulator,

the conductor upper portion partially covered by the first substrate layer and configured to form a perimeter,

a conductor base portion partially covered by the second substrate layer, and

conductor intermediate portions ex from the conductor upper portion to an upper surface of the conductor base portion forming a plurality of contacting interfaces between the conductor intermediate portions and the upper surface of the conductor base portion, wherein the contacting interfaces collectively form an exposed area on the conductor base portion, wherein the exposed area is smaller than the perimeter,

the conductor base portion in contact with a lower surface of the substrate insulator, and

the conductor intermediate portions in contact with side surfaces of the substrate insulator connected with the conductor upper portion and the conductor base portion;

an integrated circuit die over the substrate;

a die interconnect attached from the integrated circuit die to an exposed area of the conductor base portion; and

a substrate pad within the second substrate layer, the substrate pad below and in contact with the conductor base portion opposite the exposed area, an exposed bottom surface of the substrate pad is directly below the conductor base portion exposed area, the exposed bottom surface of the substrate pad is exposed from a substrate bottom surface providing electrical connectivity to a next level system.

16. The system as claimed in claim 15 wherein a die interconnect includes the die interconnect having stitch bonding or ball bonding entirely within the exposed area of the conductor base portion, the die interconnect not in contact with either the conductor intermediate portions or the conductor upper portion, and the die interconnect having a connectivity end of the die interconnect entirely over and within the exposed area of the conductor base portion.

17. The system as claimed in claim 15 wherein the substrate pad is partially exposed from the second substrate layer leaving the exposed bottom surface of the substrate pad exposed from the second substrate layer, wherein the exposed bottom surface is within a recess of the second substrate layer and above a substrate bottom surface of the second substrate layer.

18. The system as claimed in claim 15 wherein the substrate includes the conductor being connected to a substrate connector connected to the multiple layers of the substrate.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2007
From: SHIM, IL KWON; FILOTEO, DARIO S., JR.; ESPIRITU, EMMANUEL; ABINAN, RACHEL LAYDA
To: STATS CHIPPAC LTD.
Reel/Frame 019097/0940 →
Continuity (1)
Related Publication 20080237873A1 · Oct 2, 2008