IP Library Granted Patent US 8,575,018
Granted Patent B2
US 8,575,018 · App. 12/628,631 · Granted Nov 5, 2013

Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area

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Quick Facts
Patent No.
US 8,575,018
App. No.
12/628,631
Granted
Nov 5, 2013
Kind
B2
Abstract

A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Claims (74)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first insulating layer over the substrate;

forming a second conductive layer over the first conductive layer and first insulating layer;

forming an under bump metallization (UBM) layer around a bump formation area over a major surface of the second conductive layer and over side surfaces of the second conductive layer with respect to the major surface, the second conductive layer being exposed in the bump formation area;

forming a second insulating layer over the UBM layer and second conductive layer;

and

forming a bump over the second conductive layer in the bump formation area, the bump contacting the UBM layer to seal a contact interface between the bump and second conductive layer.

2. The method of claim 1 , wherein forming the UBM layer includes:

forming a third conductive layer over the second conductive layer; and

forming a fourth conductive layer over the third conductive layer, the fourth conductive layer being in contact with the bump.

3. The method of claim 2 , wherein the fourth conductive layer includes a material selected from the group consisting of aluminum, titanium, chromium, titanium nitride, and titanium tungsten.

4. The method of claim 1 , wherein forming the UBM layer includes:

forming a third conductive layer over the second conductive layer;

forming a fourth conductive layer over the third conductive layer; and

forming a fifth conductive layer over the fourth conductive layer, the fifth conductive layer being in contact with the bump.

5. The method of claim 1 , wherein the second insulating layer contacts the bump.

6. The method of claim 1 , further including forming a seed layer over the first conductive layer and first insulating layer prior to forming the second conductive layer.

7. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first insulating layer over the substrate;

forming a second conductive layer over the first conductive layer and first insulating layer;

forming a multi-layer metallization pattern around an interconnect formation area over the second conductive layer, the second conductive layer being exposed in the interconnect formation area;

forming a second insulating layer over the multi-layer metallization pattern and contacting the second conductive layer within the interconnect formation area; and

forming an interconnect structure over the second conductive layer in the interconnect formation area.

8. The method of claim 7 , wherein forming the multi-layer metallization pattern includes:

forming a third conductive layer over the second conductive layer; and

forming a fourth conductive layer over the third conductive layer, the fourth conductive layer being in contact with the interconnect structure.

9. The method of claim 8 , wherein the fourth conductive layer includes a material selected from the group consisting of aluminum, titanium, chromium, titanium nitride, and titanium tungsten.

10. The method of claim 7 , wherein forming the multi-layer metallization pattern includes:

forming a third conductive layer over the second conductive layer;

forming a fourth conductive layer over the third conductive layer; and

forming a fifth conductive layer over the fourth conductive layer, the fifth conductive layer being in contact with the interconnect.

11. The method of claim 7 , wherein the interconnect structure includes a bump.

12. The method of claim 7 , wherein the multi-layer metallization pattern covers the second conductive layer outside the interconnect formation area.

13. The method of claim 7 , further including forming a seed layer over the first conductive layer and first insulating layer prior to forming the second conductive layer.

14. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a multi-layer metallization pattern around an interconnect formation area over the first conductive layer;

forming a first insulating layer over the multi-layer metallization pattern and over the first conductive layer outside the multi-layer metallization pattern; and

forming an interconnect over the first conductive layer in the interconnect formation area.

15. The method of claim 14 , further including:

forming a second conductive layer over the substrate prior to forming the first conductive layer;

forming a second insulating layer over the substrate; and

forming a seed layer over the second conductive layer and second insulating layer.

16. The method of claim 14 , wherein forming the multi-layer metallization pattern includes:

forming a second conductive layer over the first conductive layer; and

forming a third conductive layer over the second conductive layer, the third conductive layer being in contact with the interconnect.

17. The method of claim 14 , wherein forming the multi-layer metallization pattern includes:

forming a second conductive layer over the first conductive layer;

forming a third conductive layer over the second conductive layer; and

forming a fourth conductive layer over the third conductive layer, the fourth conductive layer being in contact with the interconnect.

18. The method of claim 14 , wherein the interconnect includes a bump.

19. A semiconductor device, comprising:

a semiconductor die;

a first conductive layer formed over the semiconductor die;

a first insulating layer formed over the semiconductor die;

a second conductive layer formed over the first conductive layer and first insulating layer;

a multi-layer metallization pattern formed around an interconnect formation area over the second conductive layer;

a second insulating layer formed over the multi-layer metallization pattern and over the second conductive layer outside the multi-layer metallization pattern; and

an interconnect structure formed over the second conductive layer in the interconnect formation area.

20. The semiconductor device of claim 19 , further including:

a third conductive layer formed over the second conductive layer; and

a fourth conductive layer formed over the third conductive layer, the fourth conductive layer being in contact with the interconnect structure.

21. The semiconductor device of claim 19 , further including:

a third conductive layer formed over the second conductive layer;

a fourth conductive layer formed over the third conductive layer; and

a fifth conductive layer formed over the fourth conductive layer, the fifth conductive layer being in contact with the interconnect structure.

22. The semiconductor device of claim 19 , wherein the interconnect structure includes a bump.

23. The semiconductor device of claim 19 , wherein the multi-layer metallization pattern covers the second conductive layer outside the interconnect formation area.

24. The semiconductor device of claim 19 , further including a seed layer formed over the first conductive layer and first insulating layer prior to forming the second conductive layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2009
From: LIN, YAOJIAN; CHEN, KANG; FANG, JIANMIN
To: STATS CHIPPAC, LTD.
Reel/Frame 023587/0406 →