Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a patterned layer over the first conductive layer;

forming a second conductive layer in the patterned layer, wherein a height of the second conductive layer is greater than a height of the first conductive layer;

removing the patterned layer; and

forming a first bump and a second bump over the first and second conductive layers, respectively, wherein the second bump overlaps the first bump, and wherein an uppermost surface of the second bump is vertically offset from an uppermost surface of the first bump.

2. The method of claim 1 , wherein the patterned layer includes a photoresist layer.

3. The method of claim 1 , further including forming bond wires on the first and second bumps.

4. The method of claim 3 , wherein the bond wires are arranged in a straight configuration.

5. The method of claim 1 , wherein a pitch between the first and second conductive layers is no greater than 60 micrometers.

6. The method of claim 1 , further including forming a solder mask around the first and second conductive layers prior to forming the first and second bumps.

7. The method of claim 1 , wherein lowermost surfaces of the first conductive layer and second conductive layer are substantially coplanar.

8. A method of making a semiconductor device, comprising:

providing a substrate;

forming a plurality of first conductive layers over the substrate and including a first height;

forming a plurality of second conductive layers over the substrate interposed between the first conductive layers and including a second height differing from the first height;

forming a first interconnect structure over the first conductive layers and including a first upper surface; and

forming a second interconnect structure over the second conductive layers and including a second upper surface vertically offset from the first upper surface, wherein the second interconnect structure overlaps the first interconnect structure.

9. The method of claim 8 , wherein forming the first interconnect structure and the second interconnect structure includes forming a conductive post or a bond wire over the first and second conductive layers.

10. The method of claim 8 , wherein forming the first conductive layers includes:

forming a first patterned layer over the substrate;

forming the first conductive layers in the first patterned layer; and

removing the first patterned layer.

11. The method of claim 8 , wherein forming the second conductive layers includes:

forming a second patterned layer over the substrate;

forming the second conductive layers in the second patterned layer; and

removing the second patterned layer.

12. The method of claim 8 , further including forming bond wires on the first and second interconnect structures.

13. The method of claim 8 , further including:

forming the first conductive layers to a height no greater than 5 micrometers; and

forming the second conductive layers to a height no greater than 25 micrometers.

14. The method of claim 8 , further including forming a solder mask around the first and second conductive layers prior to forming the first and second interconnect structures.

15. A method of making a semiconductor device, comprising:

providing a substrate;

forming a plurality of first conductive layers over the substrate and including a first height;

forming a second conductive layer between the first conductive layers and including a second height differing from the first height;

forming a first interconnect structure over the first conductive layer and including a third height; and

forming a second interconnect structure over the second conductive layer and including a fourth height substantially the same as the third height.

16. The method of claim 15 , wherein forming the first and second interconnect structures includes:

forming first and second bumps over the first and second conductive layers, respectively; and

forming bond wires on the first and second bumps.

17. The method of claim 16 , wherein an upper surface of the second bump is vertically offset from an upper surface of the first bump, and wherein a width of the first bump is substantially the same as a width of the second bump.

18. The method of claim 15 , wherein forming the first conductive layers includes:

forming a first patterned layer over the substrate;

forming the first conductive layers in the first patterned layer; and

removing the first patterned layer.

19. The method of claim 15 , wherein forming the second conductive layer includes:

forming a second patterned layer over the substrate;

forming the second conductive layer in the second patterned layer; and

removing the second patterned layer.

20. The method of claim 15 , further including:

forming the first conductive layers to a height no greater than 5 micrometers; and

forming the second conductive layer to a height no greater than 25 micrometers.

21. The method of claim 16 , further including forming a solder mask around the first conductive layers and the second conductive layer prior to forming the first and second interconnect structures.

22. A semiconductor device, comprising:

a substrate;

a first conductive layer disposed over the substrate and including a first height;

a second conductive layer disposed over the substrate and including a second height differing from the first height;

a first interconnect structure disposed over the first conductive layer; and

a second interconnect structure disposed over the second conductive layer and overlapping the first interconnect structure.

23. The semiconductor device of claim 22 , wherein the first and second interconnect structures include conductive posts or bond wires formed over the first and second conductive layers.

24. The semiconductor device of claim 22 , further including a solder mask disposed around the first and second conductive layers.