IP Library Granted Patent US 8,524,538
Granted Patent B2
US 8,524,538 · App. 13/327,091 · Granted Sep 3, 2013

Integrated circuit packaging system with film assistance mold and method of manufacture thereof

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Quick Facts
Patent No.
US 8,524,538
App. No.
13/327,091
Granted
Sep 3, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.

Claims (33)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side;

mounting a mold chase having a buffer layer over the integrated circuit;

forming an encapsulation between the substrate and the buffer layer; and

removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.

2. The method as claimed in claim 1 wherein mounting the mold chase includes applying the buffer layer having a step layer greater than a surface area of the inactive side.

3. The method as claimed in claim 1 wherein mounting the mold chase includes applying the buffer layer having a barrier, the barrier in a direct contact with the non-horizontal side.

4. The method as claimed in claim 1 wherein removing the mold chase includes removing the mold chase, leaving the encapsulation having the recess surrounding the integrated circuit.

5. The method as claimed in claim 1 wherein removing the mold chase includes removing the mold chase, leaving the encapsulation having the recess at a topside of the encapsulation.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side;

mounting a mold chase having a buffer layer over the integrated circuit;

forming an encapsulation between the substrate and the buffer layer; and

removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side at a topside of the encapsulation.

7. The method as claimed in claim 6 wherein removing the mold chase includes exposing the inactive side coplanar with the topside.

8. The method as claimed in claim 6 wherein removing the mold chase includes, removing the mold chase, leaving the encapsulation having the recess with a recess surface having an uneven side.

9. The method as claimed in claim 6 wherein removing the mold chase includes, removing the mold chase, leaving the encapsulation having the recess with a recess surface having an even side.

10. The method as claimed in claim 6 wherein mounting the mold chase includes applying the buffer layer having a step layer thicker than a base layer of the buffer layer.

11. An integrated circuit packaging system comprising:

a substrate;

an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; and

an encapsulation on the integrated circuit and the substrate, the encapsulation having a recess exposing a portion of the non-horizontal side.

12. The system as claimed in claim 11 wherein the encapsulation includes the recess surrounding the integrated circuit.

13. The system as claimed in claim 11 wherein the encapsulation includes the recess at a topside of the encapsulation.

14. The system as claimed in claim 11 wherein the encapsulation exposes the inactive side.

15. The system as claimed in claim 11 wherein the encapsulation includes the recess with a recess surface having an uneven side.

16. The system as claimed in claim 11 further comprising a lower active side of the integrated circuit facing the substrate.

17. The system as claimed in claim 16 wherein the encapsulation includes the recess with a recess surface having an even side.

18. The system as claimed in claim 16 wherein the encapsulation includes the topside coplanar with the inactive side.

19. The system as claimed in claim 16 wherein the integrated circuit includes a conductive connector on a lower active side of the integrated circuit.

20. The system as claimed in claim 16 wherein the integrated circuit is a flip chip.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2012
From: LEE, JAEHYUN; JANG, KI YOUN; YU, DOKOK
To: STATS CHIPPAC LTD.
Reel/Frame 027499/0956 →