Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
View Patent ↗A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure.
1. A method of making a semiconductor device, comprising:
providing a first interconnect structure;
providing a first semiconductor die including a stress sensitive region;
disposing the first semiconductor die over the first interconnect structure including dam material between the first semiconductor die and first interconnect structure around the stress sensitive region; and
forming an encapsulant over the first semiconductor die and first interconnect structure with the dam material blocking the encapsulant from contacting the stress sensitive region.
2. The method of claim 1 , further including disposing a shielding layer or heat sink over the first semiconductor die.
3. The method of claim 1 , further including disposing a second semiconductor die over the first semiconductor die.
4. The method of claim 1 , further including forming a conductive via through the first semiconductor die.
5. The method of claim 1 , further including forming a vertical interconnect structure through the encapsulant.
6. The method of claim 1 , further including forming a second interconnect structure over the first interconnect structure or the encapsulant opposite the first interconnect structure.
7. A method of making a semiconductor device, comprising:
providing a first insulating layer;
providing a first semiconductor die including a stress sensitive region;
disposing the first semiconductor die over the first insulating layer with the stress sensitive region overlying the first insulating layer and a gap between the stress sensitive region and first insulating layer; and
depositing an encapsulant over the first semiconductor die and first insulating layer while blocking the encapsulant from contacting the stress sensitive region.
8. The method of claim 7 , further including:
forming a notch in the first insulating layer as the gap between the stress sensitive region and first insulating layer; and
disposing the first semiconductor die in contact with the first insulating layer to block the encapsulant from contacting the stress sensitive region.
9. The method of claim 7 , further including forming a dam material between the first semiconductor die and first insulating layer to block the encapsulant from contacting the stress sensitive region.
10. The method of claim 7 , further including disposing a shielding layer or heat sink over the first semiconductor die.
11. The method of claim 7 , further including forming a vertical interconnect structure through the encapsulant.
12. The method of claim 7 , further including disposing a second semiconductor die over the first semiconductor die.
13. The method of claim 7 , further including forming an interconnect structure over the first insulating layer or the encapsulant opposite the first insulating layer.
14. A semiconductor device, comprising:
a first interconnect structure;
a first semiconductor die including a stress sensitive region disposed over the first interconnect structure;
a dam material disposed between the first semiconductor die and first interconnect structure around the stress sensitive region; and
an encapsulant deposited over the first semiconductor die and first interconnect structure, wherein the dam material blocks the encapsulant from contacting the stress sensitive region.
15. The semiconductor device of claim 14 , further including a shielding layer or heat sink disposed over the first semiconductor die.
16. The semiconductor device of claim 14 , further including a second semiconductor die disposed over the first semiconductor die.
17. The semiconductor device of claim 14 , further including an underfill material disposed between the first semiconductor die and first interconnect structure.
18. The semiconductor device of claim 14 , further including a vertical interconnect structure formed through the encapsulant.
19. The semiconductor device of claim 14 , further including a second interconnect structure formed over the first interconnect structure or the encapsulant opposite the first interconnect structure.
20. A semiconductor device, comprising:
a first insulating layer;
a first semiconductor die including a stress sensitive region disposed over the first insulating layer with a gap between the stress sensitive region and first insulating layer; and
an encapsulant deposited over the first semiconductor die and first insulating layer without contacting the stress sensitive region, wherein the first insulating layer includes a notch as the gap between the stress sensitive region and first insulating layer and the first semiconductor die is disposed in contact with the first insulating layer to block the encapsulant from contacting the stress sensitive region.
21. The semiconductor device of claim 20 , further including a dam material formed between the first semiconductor die and first insulating layer to block the encapsulant from contacting the stress sensitive region.
22. The semiconductor device of claim 20 , further including a shielding layer or heat sink disposed over the first semiconductor die.
23. The semiconductor device of claim 20 , further including a vertical interconnect structure formed through the encapsulant.
24. The semiconductor device of claim 20 , further including an interconnect structure formed over the first insulating layer or the encapsulant opposite the first insulating layer.
25. A method of making a semiconductor device, comprising:
providing a first insulating layer;
providing a first semiconductor die including a stress sensitive region; and
disposing the first semiconductor die over the first insulating layer with the stress sensitive region overlying the first insulating layer and a gap between the stress sensitive region and first insulating layer.
26. The method of claim 25 , further including depositing an encapsulant over the first semiconductor die and first insulating layer.
27. The method of claim 25 , further including:
forming a notch in the first insulating layer as the gap between the stress sensitive region and first insulating layer; and
disposing the first semiconductor die in contact with the first insulating layer to block the encapsulant from contacting the stress sensitive region.
28. The method of claim 25 , further including forming a dam material between the first semiconductor die and first insulating layer to block the encapsulant from contacting the stress sensitive region.
29. The method of claim 25 , further including disposing a shielding layer or heat sink over the first semiconductor die.
30. The method of claim 25 , further including forming a vertical interconnect structure through the encapsulant.
31. The method of claim 25 , further including disposing a second semiconductor die over the first semiconductor die.
32. The method of claim 25 , further including forming an interconnect structure over the first insulating layer or the encapsulant opposite the first insulating layer.