Integrated circuit leadframe and fabrication method therefor
View Patent ↗An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.
1. A method for fabricating an integrated circuit leadframe, comprising:
forming a leadframe having leads around a die pad, the die pad includes a peripheral die pad rim;
adhering a die to the die pad;
forming a surface configuration in the peripheral die pad rim including an inner raised surface, grooves, and an outer raised surface; the inner raised surface and one of the grooves being between the die and the outer raised surface; and
attaching ground bond wire-bonds from the leads to the inner raised surface of the peripheral die pad rim, whereby the surface configuration is for providing clearance space for the ground bond wire-bonds from other wire-bonds.
2. The method of claim 1 wherein forming the surface configuration includes forming depressed separation structures.
3. The method of claim 1 wherein forming the surface configuration includes forming a sequence of discrete, alternately staggered grooves.
4. The method of claim 1 wherein forming the surface configuration includes forming X-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
5. The method of claim 1 wherein forming the surface configuration includes forming U-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
6. A method for fabricating an integrated circuit leadframe, comprising:
forming a leadframe from a single flat sheet of material in a single manufacturing process, the leadframe having leads around a die pad, the die pad includes a peripheral die pad rim;
forming a surface configuration in the peripheral die pad rim including an inner raised surface, grooves, and an outer raised surface;
adhering a semiconductor device to the die pad, the inner raised surface and one of the grooves being between the semiconductor device and the outer raised surface;
attaching ground bond wire-bonds from the leads to the inner raised surface of the peripheral die pad rim, whereby the surface configuration is for providing clearance space for the ground bond wire-bonds from other wire-bonds;
wire-bonding the semiconductor device to the leadframe; and
encapsulating at least portions of the semiconductor device and the leadframe.
7. The method of claim 6 wherein forming the surface configuration includes forming depressed separation structures.
8. The method of claim 6 wherein forming the surface configuration includes forming a sequence of discrete, alternately staggered grooves.
9. The method of claim 6 wherein forming the surface configuration includes forming X-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
10. The method of claim 6 wherein forming the surface configuration includes forming U-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
11. A leadframe for an integrated circuit, comprising:
a die pad having:
a peripheral die pad rim on the die pad, and
a surface configuration having an inner raised surface, grooves, and an outer raised surface on the peripheral die pad rim;
a die mounted on the die pad, the inner raised surface and one of the grooves being between the die and the outer raised surface;
leads around the peripheral die pad rim; and
ground bond wire-bonds attached from the leads to the inner raised surface of the peripheral die pad rim, whereby the surface configuration is for providing clearance space for the ground bond wire-bonds from other wire-bonds.
12. The leadframe of claim 11 wherein the surface configuration includes depressed separation structures.
13. The leadframe of claim 11 wherein the surface configuration includes a sequence of discrete, alternately staggered grooves.
14. The leadframe of claim 11 wherein the surface configuration includes X-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
15. The leadframe of claim 11 wherein the surface configuration includes U-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
16. A leadframe for an integrated circuit, comprising:
a die pad having:
a peripheral die pad rim on the die pad, and
a surface configuration having an inner raised surface, grooves, and an outer raised surface on the peripheral die pad rim;
a die mounted on the die pad, the inner raised surface and one of the grooves being between the die and the outer raised surface;
leads around the peripheral die pad rim;
ground bond wire-bonds attached from the leads to the inner raised surface of the peripheral die pad rim, whereby the surface configuration is for providing clearance space for the ground bond wire-bonds from other wire-bonds; and
an encapsulant encapsulating at least portions of the die and the leads.
17. The leadframe of claim 16 wherein the surface configuration includes depressed separation structures.
18. The leadframe of claim 16 wherein the surface configuration includes a sequence of discrete, alternately staggered grooves.
19. The leadframe of claim 16 wherein the surface configuration includes X-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.
20. The leadframe of claim 16 wherein the surface configuration includes U-shaped grooves for forming a discrete, alternately staggered surface configuration in the die pad.