Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices
View Patent ↗A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.
1. A semiconductor device, comprising:
a substrate;
an integrated passive device (IPD) formed over a surface of the substrate, the IPD including a capacitor;
a conductive layer formed over the surface of the substrate and electrically connected to the IPD;
a thin film layer formed over a surface of the conductive layer, the thin film layer including electrical characteristics of a varistor; and
an interconnect structure formed over a surface of the thin film layer opposite the conductive layer to provide an electrostatic discharge (ESD) path to protect the IPD from an ESD transient.
2. The semiconductor device of claim 1 , wherein the thin film layer includes metal oxide or polycrystalline/amorphous silicon.
3. The semiconductor device of claim 1 , wherein the thin film layer includes zinc oxide.
4. The semiconductor device of claim 1 , wherein the thin film layer has a resistance value as a function of a voltage applied to the thin film layer.
5. The semiconductor device of claim 1 , wherein the IPD further includes an inductor or resistor.
6. The semiconductor device of claim 1 , further including a ground interconnect structure formed over the surface of the substrate, the ground interconnect structure being a low-impedance ground point electrically connected to the conductive layer.
7. A semiconductor device, comprising:
a substrate;
an integrated passive device (IPD) susceptible to an electrostatic discharge (ESD) transient and formed over a surface of the substrate;
a first conductive layer formed over the surface of the substrate and electrically connected to the IPD;
an ESD protection structure formed over a surface of the first conductive layer
a first insulating layer formed over the ESD protection structure, IPD, and surface of the substrate; and
a bump or bond wire formed over a surface of the ESD protection structure opposite the first conductive layer and partially exposed from the first insulating layer to provide an ESD path to protect the IPD from the ESD transient.
8. The semiconductor device of claim 7 , wherein the IPD includes a capacitor, resistor, or inductor.
9. The semiconductor device of claim 7 , wherein the IPD includes:
a portion of the first conductive layer formed over the surface of the substrate;
a second insulating layer formed over the portion of the first conductive layer; and
a second conductive layer formed over the second insulating layer.
10. The semiconductor device of claim 7 , further including an insulating layer formed between the substrate and IPD.
11. The semiconductor device of claim 7 , further including a ground interconnect structure formed over the substrate and electrically connected to the first conductive layer.
12. The semiconductor device of claim 7 , wherein the ESD protection structure includes a varistor.
13. A semiconductor device, comprising:
a substrate;
a circuit structure formed over a surface of the substrate, the circuit structure being susceptible to an electrostatic discharge (ESD) transient;
a first conductive layer formed over the surface of the substrate and electrically connected to the circuit structure;
a varistor formed over a surface of the first conductive layer;
a first insulating layer formed over the varistor and circuit structure; and
an interconnect structure formed over a surface of the varistor opposite the first conductive layer and partially exposed from the first insulating layer to provide an ESD path to protect the circuit structure from the ESD transient.
14. The semiconductor device of claim 13 , wherein the varistor has a non-linear resistance as a function of a voltage applied to the varistor.
15. The semiconductor device of claim 13 , wherein the circuit structure is an integrated passive device (IPD).
16. The semiconductor device of claim 15 , wherein the IPD includes a capacitor, inductor, or resistor.
17. The semiconductor device of claim 13 , wherein the circuit structure includes:
a portion of the first conductive layer formed over the surface of the substrate;
a second insulating layer formed over the portion of the first conductive layer; and
a second conductive layer formed over the second insulating layer.
18. The semiconductor device of claim 13 , wherein the circuit structure includes a second conductive layer formed over the surface of the substrate, the second conductive layer being coiled to exhibit an inductive property.
19. The semiconductor device of claim 13 , further including a ground interconnect structure formed over the substrate and electrically connected to the first conductive layer.
20. The semiconductor device of claim 13 , wherein the interconnect structure includes a bump or bond wire.
21. A semiconductor device, comprising:
a substrate;
an integrated passive device (IPD) susceptible to an electrostatic discharge (ESD) transient and formed over a surface of the substrate;
a conductive layer formed over the surface of the substrate and electrically connected to the IPD;
a thin film layer formed over a surface of the conductive layer, wherein the thin film layer has a non-linear resistance as a function of a voltage applied to the thin film layer; and
an interconnect structure formed over a surface of the thin film layer opposite the conductive layer and partially exposed to provide an ESD path to protect the IPD from an ESD transient.
22. The semiconductor device of claim 21 , wherein the IPD includes a capacitor, resistor, or inductor.
23. The semiconductor device of claim 21 , further including a ground interconnect structure formed over the substrate and electrically connected to the conductive layer.
24. The semiconductor device of claim 21 , wherein the thin film layer includes metal oxide or polycrystalline/amorphous silicon.
25. A semiconductor device, comprising:
a substrate including an integrated passive device (IPD) susceptible to an electrostatic discharge (ESD) transient and formed over the substrate;
an interconnect structure formed over the substrate and electrically connected to the IPD;
a thin film layer formed over the substrate; and
a first conductive layer formed over the substrate, the thin film layer being electrically connected between the interconnect structure and first conductive layer to provide an ESD path to protect the IPD from the ESD transient;
wherein the IPD includes:
an insulating layer formed over the first conductive layer;
a second conductive layer formed over the insulating layer; and
a third conductive layer formed over the substrate, the third conductive layer being coiled to exhibit inductive properties.
26. A semiconductor device, comprising:
a substrate;
an integrated passive device (IPD) susceptible to an electrostatic discharge (ESD) transient and formed over a surface of the substrate;
a conductive layer formed over the surface of the substrate and electrically connected to the IPD;
a thin film layer formed over a surface of the conductive layer; and
an interconnect structure formed over a surface of the thin film layer opposite the conductive layer and partially exposed to provide an ESD path to protect the IPD from an ESD transient, wherein the interconnect structure includes a bump or bond wire.