IP Library Granted Patent US 8,557,638
Granted Patent B2
US 8,557,638 · App. 13/102,041 · Granted Oct 15, 2013

Integrated circuit packaging system with pad connection and method of manufacture thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,557,638
App. No.
13/102,041
Granted
Oct 15, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.

Claims (25)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side;

forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal;

connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and

applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.

2. The method as claimed in claim 1 wherein forming the peripheral lead includes forming the peripheral lead having the peripheral lead conductive plate with a recess at the peripheral lead bottom side.

3. The method as claimed in claim 1 further comprising forming a conductive cap directly on the peripheral lead top side.

4. The method as claimed in claim 1 wherein forming the peripheral lead includes forming the peripheral lead having a peripheral lead step portion protruding from the peripheral lead top side.

5. The method as claimed in claim 1 further comprising forming a central lead directly under the integrated circuit.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side;

forming a first top distribution layer on the peripheral lead top side;

connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of a first top terminal;

forming an encapsulation over the integrated circuit and the first top distribution layer; and

applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.

7. The method as claimed in claim 6 wherein forming the peripheral lead includes forming the peripheral lead having the peripheral lead conductive plate with a recess at the peripheral lead bottom side and with a lead plate conductive material.

8. The method as claimed in claim 6 further comprising:

forming a conductive cap directly on the peripheral lead top side; and

wherein:

forming the first top distribution layer includes forming the first top distribution layer directly on the conductive cap and having a distribution layer conductive material.

9. The method as claimed in claim 6 wherein:

forming the peripheral lead includes forming the peripheral lead having a peripheral lead step portion protruding from the peripheral lead top side; and

wherein:

forming the first top distribution layer includes forming the first top distribution layer having a peripheral distribution step portion directly on the peripheral lead step portion.

10. The method as claimed in claim 6 further comprising forming a central lead directly under the integrated circuit and adjacent the peripheral lead.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE," TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038401 FRAME: 0532. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2011
From: DO, BYUNG TAI; TRASPORTO, ARNEL SENOSA; CHUA, LINDA PEI EE
To: STATS CHIPPAC LTD.
Reel/Frame 026290/0052 →