Adhesive/spacer island structure for multiple die package
View Patent ↗An adhesive/spacer structure ( 52, 52 A, 60 ) is used to adhere first and second die ( 14, 18 ) to one another at a chosen separation in a multiple-die semiconductor chip package ( 56 ). The first and second die define a die bonding region ( 38 ) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands ( 52, 52 A) securing the first and second die to one another at a chosen separation ( 53 ). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
1. A method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising:
connecting a wire between a bond pad of a first die and a substrate with the wire having a wire loop height extending from the bond pad;
selecting an adhesive/spacer material having pliable spacer elements within an adhesive;
depositing the adhesive/spacer material onto a first surface of the first die, the adhesive/spacer material covering 20-50 percent of the first surface of the first die;
providing an electrically non-conductive second surface of a second die with a dielectric layer;
locating the second surface of the second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby:
securing the first and second die to one another at the chosen separation; and
encapsulating the first die, the second die, and the adhesive/spacer material with an encapsulating material of a filled epoxy containing 80-90 percent filler material.
2. The method according to claim 1 wherein the selecting step includes choosing spacer elements having the same size and shape.
3. The method according to claim 1 wherein the depositing step is carried out to create a plurality of generally equal-size islands of the adhesive/spacer material after the securing step.
4. The method according to claim 1 wherein the depositing step is carried out to create at least three generally equal-size islands of the adhesive/spacer material after the securing step.
5. A method for creating a multiple-die semiconductor chip package, the method comprising:
mounting a first die to a substrate, the first die having a first surface with bond pads at the first surface;
connecting the bond pads and the substrate with wires, having heights within a wire loop height extending from the bond pads;
selecting an adhesive/spacer material comprising pliable spacer elements within an adhesive;
depositing the adhesive/spacer material onto a first surface of the first die;
providing an electrically non-conductive second surface of a second surface of a second die with a dielectric layer;
locating a second surface of the second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby:
defining a die bonding region between the first and second surfaces; and
securing the first and second die to one another at a chosen separation to create a multiple-die subassembly with the adhesive/spacer material occupying a first percentage of 20-50 percent of the die bonding region; and
encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, the encapsulating material of a filled epoxy containing 80-90 percent filler material, and the wires within the die bonding region occupying a third percentage of the die bonding region.
6. The method according to claim 5 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes.
7. The method according to claim 5 wherein the depositing step includes depositing continuous expanses of adhesive/spacer material so that the first percentage is at most about 50 percent.
8. The method according to claim 5 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.
9. A method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising:
connecting a wire between a bond pad of a first die and a substrate with the wire having a wire loop height extending from the bond pad;
selecting an adhesive/spacer material having pliable spacer elements within an adhesive;
choosing an amount of the adhesive/spacer material;
depositing the chosen amount of the adhesive/spacer material onto a first surface of the first die, the adhesive/spacer material covering 20-50 percent of the first surface of the first die;
providing an electrically non-conductive second surface of a second die with a dielectric layer;
locating the second surface of the second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby:
defining a die bonding region between the first and second surfaces;
securing the first and second die to one another at the chosen separation; and
encapsulating the first die, the second die, and the adhesive/spacer material with an encapsulating material of a filled epoxy containing 80-90 percent filler material.
10. The method according to claim 9 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes.
11. The method according to claim 9 wherein the choosing step is carried out so that the adhesive/spacer material occupies about 20-50% of the die bonding region.
12. A method for creating a multiple-die semiconductor chip package, the method comprising:
mounting a first die to a substrate, the first die comprising a first surface with bond pads at the first surface;
connecting the bond pads and the substrate with wires, having heights within a wire loop height extending from the bond pads;
selecting an adhesive/spacer material having pliable spacer elements within an adhesive;
depositing the adhesive/spacer material onto a first surface of the first die to for a non-convex continuous expanse;
locating an electrically non-conductive second surface of a second die having a dielectric layer thereon opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby:
defining a die bonding region between the first and second surfaces; and
securing the first and second die to one another at a chosen separation to create a multiple-die subassembly with a first percentage of 20-50 percent of the die bonding region occupied by the adhesive/spacer material; and
encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, the encapsulating material of a filled epoxy containing 80-90 percent filler material, and the wires within the die bonding region occupying a third percentage of the die bonding region.
13. The method according to claim 12 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes.
14. The method according to claim 12 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.