Adhesive/spacer island structure for stacking over wire bonded die
View Patent ↗Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
1. A multiple-die semiconductor chip package comprising:
a substrate;
a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;
wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;
a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface;
a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple-die assembly, the adhesive/spacer islands including deformable spacer elements having a generally ellipsoidal shape and occupying a first percentage of the die bonding region;
the adhesive/spacer islands comprising at least one spacer element within an adhesive; and
a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.
2. The package according to claim 1 wherein the first percentage is between about 20-50 percent.
3. The package according to claim 1 wherein the first percentage is at most about 50%.
4. The package according to claim 1 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100 percent thereby effectively eliminating voids within the die bonding region.
5. The package according to claim 1 wherein:
the adhesive comprises epoxy; and
the encapsulating material comprises a filled epoxy.
6. The package according to claim 1 wherein the adhesive and the encapsulating material create an adhesive/encapsulating material boundary within the die bonding region.
7. A stacked semiconductor assembly comprising:
a first semiconductor device having a first surface bounded by a periphery and having bond pads at the first surface;
wires bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first device;
a package, comprising a package die mounted to and electrically interconnected with a package substrate, the package having an electrically non-conductive second surface positioned opposite the first surface, the package comprising a dielectric layer entirely covering the second surface of the package;
the first device and the package defining a first region therebetween;
an adhesive/spacer structure within the first region, the adhesive/spacer structure contacting the first and second surfaces and adhering the first device and the package to one another at a chosen separation, the adhesive/spacer structure comprising deformable spacer elements within an adhesive, and a material encapsulating the stacked assembly, the encapsulating material occupying the first region.
8. The stacked semiconductor assembly of claim 7 wherein the package is oriented so that the die attach side of the upper package substrate faces the first device.
9. The stacked semiconductor assembly of claim 7 wherein the package is oriented so that side of the upper package substrate opposite the die attach side faces the first die.
10. Stacked semiconductor packages comprising the assembly of claim 7 .
11. A multiple-die semiconductor chip package comprising:
a substrate;
a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;
wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;
a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface;
adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die assembly;
the adhesive/spacer structure comprising deformable spacer elements within an adhesive;
the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%; and
a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.
12. The package according to claim 11 wherein the first percentage is about 20-50%.
13. The package according to claim 11 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.