Flip chip interconnect solder mask
View Patent ↗A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
1. A method of making a semiconductor device, comprising:
providing a substrate including a surface which is non-wettable by solder;
forming a plurality of traces over the non-wettable surface of the substrate;
forming a masking layer over the non-wettable surface of the substrate with the traces passing beneath first and second elongated openings of the masking layer at interconnect sites and with the traces being parallel with respect to a width across the first elongated opening and being angled with respect to a width across the second elongated opening;
disposing a semiconductor die over the substrate; and
coupling the semiconductor die to the interconnect sites on the substrate.
2. The method of claim 1 , further including forming a plurality of bumps between the semiconductor die and the interconnect sites on the traces.
3. The method of claim 2 , wherein the bumps include a fusible portion and non-fusible portion.
4. The method of claim 2 , wherein the bumps include a width greater than a width of the interconnect sites.
5. A method of making a semiconductor device, comprising:
providing a substrate including first and second traces formed over a surface of the substrate; and
forming a masking layer over the surface of the substrate including first and second elongated openings with a first portion of the first and second traces passing beneath and being parallel with respect to a width across the first elongated opening and a second portion of the first and second traces passing beneath and being angled with respect to a width across the second elongated opening.
6. The method of claim 5 , further including disposing a semiconductor die over the substrate.
7. The method of claim 6 , further including forming a plurality of bumps between the semiconductor die and the interconnect sites on the first and second traces.
8. The method of claim 7 , wherein the bumps include a width greater than a width of the interconnect sites.
9. The method of claim 7 , wherein the bumps include a fusible portion and non-fusible portion.
10. The method of claim 6 , further including disposing a no-flow underfill material between the semiconductor die and substrate.