Bump-on-lead flip chip interconnection
View Patent ↗A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. [The fusible portion melts at a temperature which avoids damage to the substrate during reflow.] The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a trace including an interconnect site over a surface of the substrate;
providing a first semiconductor die;
forming a composite interconnect structure over the first semiconductor die, the composite interconnect structure including a non-collapsible portion and a collapsible portion formed over the first semiconductor die; and
disposing the first semiconductor die with the composite interconnect structure over the interconnect site.
2. The method of claim 1 , wherein a width of the interconnect site is less than or equal to 120% of a width of the trace away from the interconnect site.
3. The method of claim 1 , further including deforming the collapsible portion over the interconnect site by applying force.
4. The method of claim 1 , wherein the substrate includes a second semiconductor die.
5. The method of claim 1 , wherein the substrate includes a printed circuit board.
6. The method of claim 1 , further including forming an insulating layer over the surface of the substrate.
7. The method of claim 1 , further including forming an adhesive over the substrate and interconnect site.
8. The method of claim 7 , further including pressing the composite interconnect structure over the interconnect site to displace the adhesive from between the composite interconnect structure and the interconnect site.
9. The method of claim 8 , further including:
heating the adhesive to partially cure the adhesive; and
heating the composite interconnect structure and adhesive to melt the collapsible portion of the composite interconnect structure and to completely cure the adhesive.
10. A method of making a semiconductor device, comprising:
providing a substrate;
forming a trace including an interconnect site over a surface of the substrate;
forming a composite interconnect structure including a collapsible portion and a non-collapsible portion; and
disposing the composite interconnect structure over the interconnect site of the trace by applying force to deform the collapsible portion over the interconnect site.
11. The method of claim 10 , further including forming an insulating layer including an opening disposed over the interconnect site over the trace.
12. The method of claim 10 , further including forming the interconnect site of the trace including a width less than a width of the composite interconnect structure.
13. The method of claim 10 , wherein the substrate includes a printed circuit board.
14. The method of claim 10 , wherein the substrate includes a semiconductor die.
15. The method of claim 10 , further including:
providing a first semiconductor die; and
forming the composite interconnect structure over a surface of the first semiconductor die.
16. The method of claim 15 , wherein the substrate includes a second semiconductor die.
17. The method of claim 10 , further including reflowing the composite interconnect structure after deforming the collapsible portion over the interconnect site.
18. A semiconductor device, comprising:
a substrate;
a trace including an interconnect site formed over the substrate; and
an interconnect structure disposed directly on the interconnect site of the trace and including a width greater than a width of the interconnect site of the trace; and
an adhesive formed over the substrate, wherein the interconnect structure is pressed into the adhesive to displace the adhesive between the interconnect structure and the interconnect site.
19. The semiconductor device of claim 18 , wherein the width of the interconnect site is less than or equal to 120% of a width of the trace away from the interconnect site.
20. The semiconductor device of claim 18 , wherein the interconnect structure includes a non-collapsible portion and a collapsible portion.
21. The semiconductor device of claim 18 , wherein the substrate includes a printed circuit board.
22. The semiconductor device of claim 18 , wherein the substrate includes a semiconductor die.
23. The semiconductor device of claim 18 , further including a first semiconductor die disposed over the interconnect structure.
24. The semiconductor device of claim 23 , wherein the substrate includes a second semiconductor die.