Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
View Patent ↗A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V SS and forms a ground plane. A second portion of the first conductive layer is electrically connected to V DD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.
1. A semiconductor device, comprising:
a semiconductor die;
a first ground plane including a first side surface extending laterally along an entire length of a first side surface of the semiconductor die outside a footprint of the semiconductor die;
a second ground plane including a first side surface extending laterally along an entire length of a second side surface of the semiconductor die and further extending laterally along a length of the first side surface of the first ground plane; and
a conductive layer formed over the semiconductor die and extending to the first ground plane outside the footprint of the semiconductor die.
2. The semiconductor device of claim 1 , further including a substrate comprising a plurality of vertical interconnect structures formed through the substrate disposed adjacent to the semiconductor die.
3. The semiconductor device of claim 2 , wherein the first ground plane is formed over the substrate.
4. The semiconductor device of claim 1 , further including a power plane disposed adjacent to the semiconductor die.
5. The semiconductor device of claim 1 , further including a dummy die disposed adjacent to the first side surface of the semiconductor die, wherein the first ground plane is formed over the dummy die.
6. The semiconductor device of claim 1 , further including an insulating layer disposed between the first ground plane and the conductive layer, wherein the first ground plane, insulating layer, and conductive layer form a capacitor.