Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
View Patent ↗A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a plurality of openings into a first surface of the semiconductor die;
depositing an insulating material over sidewalls of the openings;
depositing a conductive material into the openings of the semiconductor die to form a plurality of conductive vias in the semiconductor die;
planarizing a second surface of the semiconductor die to remove a portion of the insulating material and expose a top horizontal surface of the conductive vias;
applying a first insulating layer selectively onto the second surface of the semiconductor die across an entire width of the semiconductor die except for the top horizontal surfaces of the conductive vias, wherein the second surface of the semiconductor die remains coplanar with the top horizontal surface of the conductive vias while applying the first insulating layer; and
forming a first solder bump on the top horizontal surface of one of the conductive vias and extending into an opening of the first insulating layer, wherein forming the first solder bump is after depositing the conductive material to form the plurality of conductive vias and planarizing the second surface of the semiconductor die.
2. The method of claim 1 , further including forming the first insulating layer using oxidation of the semiconductor die.
3. The method of claim 1 , further including forming an under bump metallization over the first insulating layer and into the opening of the first insulating layer to contact the top horizontal surface of the conductive vias.
4. The method of claim 1 , further including forming the first solder bump over a plurality of the conductive vias and extending into a plurality of openings of the insulating layer.
5. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a plurality of conductive vias in the semiconductor die;
planarizing the semiconductor die and conductive vias to leave a surface of the semiconductor die that is coplanar with a top horizontal surface of each of the conductive vias;
applying a first insulating layer laterally over an entire width of the surface of the semiconductor die except for the top horizontal surfaces of the conductive vias after forming the plurality of conductive vias, wherein a length of the conductive vias in a thickness direction is greater than a length of the semiconductor die in a thickness direction; and
forming an interconnect structure on the top horizontal surfaces of the conductive vias within a height of the first insulating layer after applying the first insulating layer.
6. The method of claim 5 , further including forming the first insulating layer using electrografting.
7. The method of claim 5 , further including forming an under bump metallization over the conductive via.
8. The method of claim 5 , further including removing a portion of the semiconductor die to expose the conductive via.
9. The method of claim 5 , further including forming the interconnect structure over a plurality of conductive vias.
10. The method of claim 5 , further including forming the conductive via with a height greater than a height of the semiconductor die.
11. The method of claim 5 , further including:
forming a second insulating layer over the first insulating layer; and
removing a portion of the second insulating layer to expose the top horizontal surface of the conductive via.
12. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a conductive via in the semiconductor die including a top horizontal surface of the conductive via coplanar with the semiconductor die; and
applying a first insulating layer selectively over an entire width of the semiconductor die while the conductive via remains coplanar with the semiconductor die, wherein the first insulating layer includes an opening in the first insulating layer over the top horizontal surface of the conductive via.
13. The method of claim 12 , further including forming the first insulating layer using electrografting or oxidation.
14. The method of claim 12 , further including removing a portion of the semiconductor die to expose the top horizontal surface of the conductive via.
15. The method of claim 12 , further including forming an interconnect structure over a plurality of conductive vias.
16. The method of claim 12 , further including:
forming a second insulating layer over the first insulating layer; and
removing a portion of the second insulating layer to expose the conductive via.
17. A method of making a semiconductor device, comprising:
providing a substrate;
forming a conductive via in the substrate;
removing a portion of the substrate to expose a top horizontal surface of the conductive via; and
forming a first insulating layer selectively across an entire width of the substrate to include an opening in the first insulating layer over the top horizontal surface of the conductive via.
18. The method of claim 17 , further including forming the first insulating layer using electrografting or oxidation.
19. The method of claim 17 , further including forming an under bump metallization over the conductive via.
20. The method of claim 17 , further including forming an interconnect structure over a plurality of conductive vias.
21. The method of claim 17 , further including:
forming a second insulating layer over the first insulating layer; and
removing a portion of the second insulating layer to expose the conductive via.
22. The method of claim 1 , further including:
forming a plurality of second solder bumps on the conductive vias;
disposing the semiconductor die on a carrier with the second solder bumps extending from the conductive vias to the carrier;
depositing an underfill material between the semiconductor die and carrier around the second solder bumps; and
planarizing the second surface of the semiconductor die while the semiconductor die remains on the carrier.
23. The method of claim 22 , further including singulating the semiconductor die from a semiconductor wafer after forming the first solder bump while the semiconductor die remains on the carrier.
24. The method of claim 1 , further including:
depositing a second insulating layer over the first insulating layer opposite the semiconductor die and in direct physical contact with the top horizontal surface of the conductive via;
removing a portion of the second insulating layer to form an opening through the second insulating layer and expose the top horizontal surface of the conductive via; and
forming the first solder bump extending into the opening of the first insulating layer and the opening of the second insulating layer.
25. The method of claim 1 , further including forming the first insulating layer extending continuously across the entire width of the semiconductor die.