IP Library Granted Patent US 9,472,452
Granted Patent B2
US 9,472,452 · App. 14/284,752 · Granted Oct 18, 2016

Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

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Quick Facts
Patent No.
US 9,472,452
App. No.
14/284,752
Granted
Oct 18, 2016
Kind
B2
Abstract

A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Claims (56)

1. A method of making a semiconductor device, comprising:

providing a semiconductor die including a first conductive layer;

forming a first insulating layer over the semiconductor die and first conductive layer;

forming an opening in the first insulating layer over the first conductive layer;

forming a second insulating layer over the first insulating layer; and

forming a via in the second insulating layer over the first conductive layer, wherein a width of the via is less than a width of the opening in the first insulating layer.

2. The method of claim 1 , further including forming a second conductive layer over the first conductive layer.

3. The method of claim 1 , further including:

forming a third insulating layer over the second insulating layer; and

forming a second conductive layer over the third insulating layer.

4. The method of claim 3 , further including forming an opening in the third insulating layer and including a width greater than a width of the via.

5. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over the semiconductor die;

forming a second insulating layer over the first insulating layer and within an opening in the first insulating layer; and

forming a via in the second insulating layer.

6. The method of claim 5 , further including forming the via over a contact pad of the semiconductor die.

7. The method of claim 5 , further including:

forming a first conductive layer over the semiconductor die; and

forming a second conductive layer over the first conductive layer.

8. The method of claim 5 , further including disposing a conductive layer in the via.

9. The method of claim 5 , further including:

forming a third insulating layer over the second insulating layer; and

forming a conductive layer over the third insulating layer.

10. The method of claim 5 , further including:

depositing an encapsulant over the semiconductor die; and

forming a conductive layer within the via and over the encapsulant.

11. A method of making a semiconductor device, comprising:

providing a substrate including a first conductive layer;

forming a first insulating layer over the substrate;

forming a second insulating layer over the first conductive layer and within an opening in the first insulating layer; and

forming a via in the second insulating layer over the first conductive layer.

12. The method of claim 11 , further including disposing a second conductive layer within the via.

13. The method of claim 11 , further including forming a second conductive layer over the first conductive layer.

14. The method of claim 11 , further including:

forming a third insulating layer over the second insulating layer;

forming an opening in the third insulating layer over the via; and

forming a second conductive layer over the third insulating layer.

15. The method of claim 11 , wherein a width of the via is less than a width of the first conductive layer.

16. The method of claim 11 , wherein the substrate includes a semiconductor die.

17. The method of claim 11 , wherein a width of the via is less than a width of the opening in the first insulating layer.

18. The method of claim 1 , further including forming a second conductive layer over the via, wherein a width of the second conductive layer is greater than a width of the via.

19. The method of claim 1 , further including forming an interconnect structure over the via.

20. The method of claim 5 , wherein a width of the via is less than a width of the opening in the first insulating layer.

21. A method of making a semiconductor device, comprising:

forming a first conductive layer;

forming a first insulating layer over the first conductive layer;

forming a second insulating layer over the first conductive layer and first insulating layer;

forming a via in the second insulating layer over the first conductive layer; and

forming a second conductive layer over the second insulating layer and within the via.

22. The method of claim 21 , wherein forming the first conductive layer includes forming the first conductive layer over a semiconductor die as a contact pad of the semiconductor die.

23. The method of claim 21 , further including forming an opening in the first insulating layer, wherein the width of the via is less than a width of the opening in the first insulating layer.

24. The method of claim 21 , further including:

forming a third insulating layer over the second insulating layer; and

forming an opening in the third insulating layer over the via.

25. The method of claim 24 , wherein a width of the opening in the third insulating layer is greater than a width of the via.

Assignments (5)
THIS SUBMISSION IS TO CORRECT A TYPOGRAPHICAL ERROR IN THE COVER SHEET PREVIOUSLY RECORDED ON REEL: 038378 FRAME: 0382 TO CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." Recorded Sep 6, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064869/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0382 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →