Semiconductor device and method of forming through mold hole with alignment and dimension control
View Patent ↗A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over a first surface of the semiconductor die and around the semiconductor die;
forming a first insulating layer over a second surface of the semiconductor die opposite the first surface;
forming a plurality of conductive vias through the first insulating layer;
forming an interconnect structure over the semiconductor die and encapsulant; and
forming a first opening in the encapsulant extending to the conductive vias.
2. The method of claim 1 , further including forming a conductive bump within the first opening.
3. The method of claim 1 , further including:
inspecting the conductive vias through the first opening; and
adjusting the semiconductor device based on a position of the conductive vias.
4. The method of claim 1 , further including inspecting the conductive vias through the first opening to measure a dimension of the first opening.
5. The method of claim 1 , further including determining a position of the conductive vias in the first opening.
6. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over the semiconductor die;
forming a conductive via array over the encapsulant outside a footprint of the semiconductor die;
forming a first opening in the encapsulant extending to the conductive via array; and
determining a position of the conductive via array in the first opening.
7. The method of claim 6 , further including forming an interconnect structure over the semiconductor die and encapsulant.
8. The method of claim 6 , further including forming a conductive material within the first opening.
9. The method of claim 6 , further including:
inspecting the conductive via array through the first opening; and
adjusting the semiconductor device based on the position of the conductive via array.
10. The method of claim 6 , further including inspecting the conductive via array through the first opening to measure a dimension of the first opening.
11. The method of claim 6 , further including forming the conductive via array in a circular or hexagonal pattern.
12. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die;
a plurality of first conductive vias formed over the encapsulant; and
an opening formed through the encapsulant extending to the first conductive vias.
13. The semiconductor device of claim 12 , further including an interconnect structure formed over the semiconductor die and encapsulant.
14. The semiconductor device of claim 12 , further including a bump formed in the opening over the first conductive vias.
15. The semiconductor device of claim 12 , further including a conductive pad formed over the first conductive vias.
16. The semiconductor device of claim 12 , further including a plurality of second conductive vias formed adjacent to the first conductive vias over the encapsulant.
17. The semiconductor device of claim 16 , wherein the first conductive vias are disposed in a staggered pattern.
18. The semiconductor device of claim 12 , further including a conductive layer formed over the semiconductor die electrically connected to the first conductive vias.
19. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die;
a conductive via array formed over the encapsulant outside a footprint of the semiconductor die;
an opening formed in the encapsulant over the conductive via array; and
a conductive pad formed over the conductive via array.
20. The semiconductor device of claim 19 , further including a bump formed in the opening over the conductive via array.
21. The semiconductor device of claim 19 , wherein the conductive via array includes a plurality of conductive vias in a staggered position over the conductive pad.
22. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
depositing an encapsulant over the first semiconductor die;
forming a plurality of conductive vias over the encapsulant; and
forming a first opening in the encapsulant extending to the conductive vias.
23. The method of claim 22 , further including:
providing a second semiconductor die; and
depositing the encapsulant over the second semiconductor die.
24. The method of claim 22 , further including depositing a conductive material in the first opening.
25. The method of claim 22 , further including:
inspecting the conductive vias through the first opening; and
forming a second opening in the encapsulant based on a position of the conductive vias in the first opening.
26. The method of claim 22 , further including forming a conductive pad over the conductive vias.
27. The method of claim 22 , further including forming the plurality of conductive vias in a staggered position.
28. The method of claim 22 , further including determining an alignment of the first opening by inspecting the conductive vias through the first opening.
29. The method of claim 22 , further including determining a dimension of the first opening by inspecting the conductive vias through the first opening.