Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
View Patent ↗A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.
1. A semiconductor device, comprising:
a substrate including a plurality of trace lines;
a mask patch disposed between the trace lines; and
an interconnect structure disposed over a trace line from the plurality of trace lines.
2. The semiconductor device of claim 1 , wherein the trace lines include integrated bump pads that are co-linear with the trace lines and the mask patch is formed between the integrated bump pads.
3. The semiconductor device of claim 1 , further including a semiconductor die disposed over the substrate.
4. The semiconductor device of claim 1 , wherein the mask patch is isolated and formed within an array of integrated bump pads on the trace lines.
5. The semiconductor device of claim 1 , wherein the interconnect structure includes a non-fusible portion and fusible portion.
6. The semiconductor device of claim 1 , wherein the mask patch confines the interconnect structure on one of the trace lines.
7. A semiconductor device, comprising:
a substrate including a plurality of trace lines comprising integrated bump pads; and
a plurality of isolated mask patches formed around the integrated bump pads.
8. The semiconductor device of claim 7 , further including a semiconductor die disposed over the substrate.
9. The semiconductor device of claim 7 , further including an interconnect structure formed over an integrated bump pad from the integrated bump pads.
10. The semiconductor device of claim 9 , wherein the interconnect structure includes a fusible portion and a non-fusible portion.
11. The semiconductor device of claim 7 , further including an array of the integrated bump pads with the isolated mask patches formed interstitially within the array of the integrated bump pads.
12. The semiconductor device of claim 11 , wherein the integrated bump pads are formed co-linear with the trace lines and the mask patches are formed between the integrated bump pads.
13. A semiconductor device, comprising:
a substrate including a plurality of trace lines; and
a plurality of isolated mask patches disposed between the trace lines.
14. The semiconductor device of claim 13 , further including a semiconductor die disposed over the substrate.
15. The semiconductor device of claim 13 , further including an interconnect structure disposed over one of the trace lines.
16. The semiconductor device of claim 15 , wherein the interconnect structure includes a non-fusible portion and fusible portion.
17. The semiconductor device of claim 15 , wherein the isolated mask patches confine the interconnect structure around the integrated bump pads.
18. The semiconductor device of claim 13 , further including an array of bump pads integrated in the trace lines with the isolated mask patches formed interstitially within the bump pads.
19. The semiconductor device of claim 13 , wherein the integrated bump pads are co-linear with the trace lines and the isolated mask patches are formed between the integrated bump pads.
20. A semiconductor device, comprising:
a substrate including a plurality of trace lines; and
a plurality of mask patches formed between trace lines.
21. The semiconductor device of claim 20 , further including a semiconductor die disposed over the substrate.
22. The semiconductor device of claim 20 , further including an interconnect structure formed over the plurality of trace lines.
23. The semiconductor device of claim 22 , wherein the interconnect structure further includes forming a non-fusible portion and fusible portion.
24. The semiconductor device of claim 20 , further including an array of integrated bump pads on the trace lines with the mask patches interstitially within the array of integrated bump pads.
25. The semiconductor device of claim 24 , wherein the integrated bump pads are co-linear with the trace lines and the mask patches are formed between the integrated bump pads.