Patent Assignment
Reel/Frame 040142/0234
Assignment of Assignor's Interest
Recorded: 2016-10-26
Pages: 6
Assignors
CHIANG, KATHERINE
Executed: 2016-07-12
HSIAO, CHENG
Executed: 2016-07-12
HUANG, CHANG-YU
Executed: 2016-07-12
CHEN, JUAN YI
Executed: 2016-07-12
SU, KE-WEI
Executed: 2016-07-12
LIN, CHUNG-KAI
Executed: 2016-07-18
CHANG, LESTER
Executed: 2016-07-12
JENG, MIN-CHIE
Executed: 2016-07-18
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77, TAIWAN
Covered Property
(1)
Method and System for Integrated Circuit Design With On-Chip Variation and Spatial Correlation