IP Library › Assignment 042459/0920
Patent Assignment
Reel/Frame 042459/0920

Assignment of Assignor's Interest

Recorded: 2017-05-22 Pages: 4
Assignors
HSIEH, SHANG-CHIH
Executed: 2016-09-26
ZHUANG, HUI-ZHONG
Executed: 2014-09-26
CHIANG, TING-WEI
Executed: 2016-09-28
CHEN, CHUN-FU
Executed: 2016-09-28
TSENG, HSIANG-JEN
Executed: 2014-09-26
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. VI, HSINCHU SCIENCE PARK, HSINCHU, 300, TAIWAN
Covered Property (1)
System for Designing Integrated Circuit Layout and Method of Making the Integrated Circuit Layout
Application: 15/601,697 →
Publication: US 2017/0255739
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Corrective Assignment to Correct the Execution Date (S) of the Inventors Previously Recorded at Reel: 042459 Frame: 0920. Assignor(S) Hereby Confirms the Assignment . Jun 5, 2017
From: HSIEH, SHANG-CHIH; ZHUANG, HUI-ZHONG; CHIANG, TING-WEI; CHEN, CHUN-FU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 042757/0097 →