System for designing integrated circuit layout and method of making the integrated circuit layout
An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
1. A method of generating an integrated circuit layout, comprising:
receiving, by a hardware processor, a layout of a standard cell, the standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch;
placing the layout of the standard cell for the integrated circuit layout, all input/output signal ports of the standard cell overlapping a first set of a plurality of virtual grid lines; and
placing layout patterns of one or more metal lines for the integrated circuit layout, the layout patterns of the one or more metal lines overlapping a second set of the plurality of virtual grid lines,
the plurality of virtual grid lines being in parallel, and two adjacent lines of the plurality of virtual grid lines being separated by the nominal minimum pitch.
2. The method of claim 1 , wherein a ratio of the cell height to the nominal minimum pitch ranges from 6 to 16.
3. The method of claim 2 , wherein the ratio of the cell height to the nominal minimum pitch is 7.5.
4. The method of claim 1 , wherein a ratio of the cell height to the nominal minimum pitch is p/q, and p and q are integers.
5. The method of claim 1 , wherein the standard cell is a logic gate cell.
6. The method of claim 5 , wherein the logic gate cell is an AND, OR, NAND, NOR, XOR, AOI, OAI, MUX, Flip-flop, BUFF, Latch, INV, delay, or clock cell.
7. The method of claim 1 , further comprising manufacturing an integrated circuit using the integrated circuit layout.