Patent Assignment
Reel/Frame 042702/0460
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-06-14
Received: 2017-06-14
Pages: 8
Assignor
SPANSION LLC
Executed: 2017-05-19
Assignee
ADVANCED MICRO DEVICES, INC.
ONE AMD PLACE, P.O. BOX 3453, SUNNYVALE, CA, 94088, UNITED STATES
Covered Applications
(26)
INTEGRATED CIRCUIT WITH METAL AND SEMI-CONDUCTING GATE
App. No. 13/644,387
→
METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
App. No. 13/044,313
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SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
App. No. 12/910,331
→
QUASI-RESONANT VALLEY VOLTAGE DETECTING METHOD AND APPARATUS
App. No. 12/482,358
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CURRENT-LEVEL CONTROLLING DEVICE FOR A POWER SUPPLY DEVICE AND RELATED POWER SUPPLY DEVICE
App. No. 12/336,537
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METHOD FOR IMPROVED PLANARIZATION IN SEMICONDUCTOR DEVICES
App. No. 11/616,563
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INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE
App. No. 11/611,856
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CU ANNEALING FOR IMPROVED DATA RETENTION IN FLASH MEMORY DEVICES
App. No. 11/593,086
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MEMORY CELL SYSTEM WITH CHARGE TRAP
App. No. 11/458,046
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METHODS FOR FABRICATING FLASH MEMORY DEVICES
App. No. 11/412,365
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METHOD FOR DECREASING SHEET RESISTIVITY VARIATIONS OF AN INTERCONNECT METAL LAYER
App. No. 11/388,390
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MEMORY CELL SYSTEM USING SILICON-RICH NITRIDE
App. No. 11/277,008
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ENHANCED ETCHING OF A HIGH DIELECTRIC CONSTANT LAYER
App. No. 11/371,024
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SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND COMPOSITE SILICON NITRIDE CAPPING LAYERS
App. No. 11/356,311
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INTEGRATED CIRCUIT CONTACT SYSTEM
App. No. 11/286,173
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METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
App. No. 11/235,214
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SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
App. No. 11/193,409
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SYSTEM AND METHOD FOR IMPROVING RELIABILITY IN A SEMICONDUCTOR DEVICE
App. No. 11/186,969
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INTERFACE LAYER BETWEEN DUAL POLYCRYSTALLINE SILICON LAYERS
App. No. 11/135,492
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MEMORY CELL HAVING COMBINATION RAISED SOURCE AND DRAIN AND METHOD OF FABRICATING SAME
App. No. 11/112,884
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MEMORY DEVICE HAVING A NANOCRYSTAL CHARGE STORAGE REGION AND METHOD
App. No. 11/065,388
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METAL/OXIDE ETCH AFTER POLISH TO PREVENT BRIDGING BETWEEN ADJACENT FEATURES OF A SEMICONDUCTOR STRUCTURE
App. No. 11/000,870
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UTILIZATION OF A TA-CONTAINING CAP OVER COPPER TO FACILITATE CONCURRENT FORMATION OF COPPER VIAS AND MEMORY ELEMENT STRUCTURES
App. No. 10/988,239
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SEMICONDUCTOR DEVICE WITH ELECTRICALLY BIASED DIE EDGE SEAL
App. No. 10/976,876
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METHOD OF MAKING A SEMICONDUCTOR STRUCTURE
App. No. 10/939,775
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SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
App. No. 10/928,665
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