IP Library Granted Patent US 7,135,396
Granted Patent B1
US 7,135,396 · App. 10/939,775 · Granted Nov 14, 2006

Method of making a semiconductor structure

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Quick Facts
Patent No.
US 7,135,396
App. No.
10/939,775
Granted
Nov 14, 2006
Kind
B1
Abstract

Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Claims (27)

1. A method of processing a semiconductor structure, comprising:

forming a refractory metal layer over a substrate comprising copper, the refractory metal layer comprising at least one selected form a group consisting of W, TiW, Ta, and TaN;

forming a semiconductor layer over the refractory metal layer; and

removing a portion of the refractory metal layer and the semiconductor layer formed on the substrate layer by etching using a fluorine-containing compound, wherein the copper in the substrate is substantially unetched by the fluorine-containing compound.

2. The method of claim 1 , wherein the substrate layer further comprises a dielectric material or semiconductor material.

3. The method of claim 2 , wherein the opening is a via, trench, or line.

4. The method of claim 1 , wherein the substrate comprises copper in an opening therein.

5. The method of claim 1 , wherein the substrate comprises copper in a layer therein.

6. The method of claim 1 , wherein the semiconductor layer comprises a Group IV semiconductor, a Group III-V semiconductor, or a Group II-VI semiconductor.

7. The method of claim 1 , wherein the semiconductor layer comprises Ge.

8. The method of claim 1 , wherein the refractory metal layer comprises TiW and the semiconductor layer comprises Ge.

9. The method of claim 1 , wherein removing the portion of the refractory metal layer and the semiconductor layer is carried out by plasma etching, reactive ion etching, or ion-enhanced etching.

10. The method of claim 1 , wherein the fluorine-containing compound comprises at least one selected from the group consisting of a fluorinated carbon, a fluorinated hydrocarbon, sulfur hexafluoride, silicon tetrafluoride, and nitrogen trifluoride.

11. A method of making a diode, comprising:

providing a substrate layer having a copper portion therein;

forming a refractory metal layer over the substrate layer, the refractory metal layer comprising at least one selected from the group consisting of W, TiW, Ta, and TaN;

forming a semiconductor layer over the refractory metal layer; and

removing a portion of the refractory metal layer and the semiconductor layer formed on the substrate layer by etching using a fluorine-containing compound, wherein the copper in the substrate is substantially unetched by the fluorine-containing compound.

12. The method of claim 11 , wherein the substrate layer further comprises a dielectric material or semiconductor material.

13. The method of claim 12 , wherein the opening is a via, trench, or line in the substrate layer.

14. The method of claim 11 , wherein the copper portion comprises an opening in the substrate layer.

15. The method of claim 11 , wherein the copper portion comprises a layer in the substrate layer.

16. The method of claim 11 , wherein the semiconductor layer comprises a Group IV semiconductor, a Group III-V semiconductor, or a Group II-VI semiconductor.

17. The method of claim 11 , wherein the semiconductor layer comprises Ge.

18. The method of claim 11 , wherein the refractory metal layer comprises TiW and the semiconductor layer comprises Ge.

19. The method of claim 11 , wherein removing the portion of the refractory metal layer and the semiconductor layer is carried out by plasma etching, reactive ion etching, or ion-enhanced etching.

20. The method of claim 11 , wherein the fluorine-containing compound comprises at least one selected from the group consisting of a fluorinated carbon, a fluorinated hydrocarbon, sulfur hexafluoride, silicon tetrafluoride, and nitrogen trifluoride.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2017
From: SPANSION LLC
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 042702/0460 →
RELEASE OF SECURITY INTEREST Recorded May 17, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 042486/0315 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 015792 FRAME 0830. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Mar 28, 2005
From: SHIELDS, JEFFREY
To: SPANSION LLC
Reel/Frame 015826/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2004
From: GABRIEL, CALVIN T.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 015792/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2004
From: SHIELDS, JEFFREY
To: SPANSION, LLC
Reel/Frame 015792/0830 →