Patent Assignment
Reel/Frame 042486/0315
Release of Security Interest
Recorded: 2017-05-17
Received: 2017-05-17
Pages: 7
Assignor
MORGAN STANLEY SENIOR FUNDING, INC.
Executed: 2017-05-09
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134-1709, UNITED STATES
Covered Properties
(24)
Integrated Circuit with Metal and Semi-Conducting Gate
Application:
13/644,387 →
Method for Forming Narrow Structures in a Semiconductor Device
Application:
13/044,313 →
System and Method for Improving Mesa Width in a Semiconductor Device
Application:
12/910,331 →
Method for Improved Planarization in Semiconductor Devices
Application:
11/616,563 →
Integrated Circuit System with Metal and Semi-Conducting Gate
Application:
11/611,856 →
Cu Annealing for Improved Data Retention in Flash Memory Devices
Application:
11/593,086 →
Memory Cell System with Charge Trap
Application:
11/458,046 →
Methods for Fabricating Flash Memory Devices
Application:
11/412,365 →
Method for Decreasing Sheet Resistivity Variations of an Interconnect Metal Layer
Application:
11/388,390 →
Memory Cell System Using Silicon-Rich Nitride
Application:
11/277,008 →
Enhanced Etching of a High Dielectric Constant Layer
Application:
11/371,024 →
Semiconductor Devices with Copper Interconnects and Composite Silicon Nitride Capping Layers
Application:
11/356,311 →
Integrated Circuit Contact System
Application:
11/286,173 →
Method for Forming Narrow Structures in a Semiconductor Device
Application:
11/235,214 →
System and Method for Improving Mesa Width in a Semiconductor Device
Application:
11/193,409 →
System and Method for Improving Reliability in a Semiconductor Device
Application:
11/186,969 →
Interface Layer Between Dual Polycrystalline Silicon Layers
Application:
11/135,492 →
Memory Cell Having Combination Raised Source and Drain and Method of Fabricating Same
Application:
11/112,884 →
Memory Device Having a Nanocrystal Charge Storage Region and Method
Application:
11/065,388 →
Metal/Oxide Etch After Polish to Prevent Bridging Between Adjacent Features of a Semiconductor Structure
Application:
11/000,870 →
Utilization of a Ta-Containing Cap Over Copper to Facilitate Concurrent Formation of Copper Vias and Memory Element Structures
Application:
10/988,239 →
Semiconductor Device with Electrically Biased Die Edge Seal
Application:
10/976,876 →
Method of Making a Semiconductor Structure
Application:
10/939,775 →
Semiconductor Component Having a Contact Structure and Method of Manufacture
Application:
10/928,665 →