Method for improved planarization in semiconductor devices

1. A method, comprising:

forming a silicon oxynitride mask layer over a first layer;

etching the first layer using the silicon oxynitride mask layer, to form a pattern in the first layer;

filling the pattern with a dielectric material to form a dielectric layer;

polishing the dielectric material with a silica-based slurry for a first predetermined period of time at a first polishing rate; and

polishing, at a second polishing rate that is faster than the first polishing rate, the dielectric material with a ceria-based slurry for a second predetermined period of time using the silicon oxynitride mask layer as a stop layer following the polishing the dielectric material with the silica-based slurry.

2. The method of claim 1 , where the silicon oxynitride mask layer comprises an anti-reflective layer.

3. The method of claim 1 , where the dielectric layer comprises an oxide layer.

4. The method of claim 1 , where the silicon oxynitride mask layer has a thickness ranging from about 100 Å to about 500 Å.

5. The method of claim 1 , where the first layer comprises at least a substrate layer.

6. The method of claim 5 , where the first layer further comprises a second dielectric layer formed over the substrate layer.

7. The method of claim 6 , where the second dielectric layer comprises a nitride layer.

8. The method of claim 5 , where the pattern in the first layer comprises a trench in the substrate layer.

9. The method of claim 8 , where the dielectric layer comprises a field oxide layer.

10. The method of claim 9 , further comprising:

selectively removing the silicon oxynitride mask layer; and

forming at least two charge storage elements over the substrate layer on opposite sides of the trench.

11. The method of claim 1 , further comprising:

forming a second layer over the first layer, where the first layer comprises a substrate layer and the second layer comprises a sacrificial nitride layer formed over the substrate layer.

12. The method of claim 11 , further comprising:

selectively removing the sacrificial nitride layer; and

forming a gate structure over the substrate layer.

13. The method of claim 12 , where the etching the first layer comprises forming a pattern in the gate structure.

14. The method of claim 11 , where the dielectric layer is a bitline oxide layer.

15. A method for fabricating a semiconductor device, comprising:

forming a first dielectric layer over a substrate;

forming a second dielectric layer over the first dielectric layer;

forming a silicon oxynitride mask layer over the second dielectric layer;

forming a photoresist layer over the silicon oxynitride mask layer;

patterning the photoresist layer to define mask regions;

etching the silicon oxynitride mask layer to form a silicon oxynitride mask;

etching the substrate, the first dielectric layer, and the second dielectric layer to form at least one isolation trench in a portion of the substrate not covered by the silicon oxynitride mask;

filling the trench with a dielectric material;

polishing the dielectric material with a silica-based slurry for a first predetermined period of time and at a first polishing rate;

polishing, at a second polishing rate that is faster than the first polishing rate, the dielectric material with a ceria-based slurry for a second predetermined period of time using the silicon oxynitride mask layer as a stop layer following the polishing the dielectric material with the silica-based slurry;

stripping the silicon oxynitride mask from the semiconductor device;

forming a third dielectric layer over the second dielectric layer and the dielectric material; and

forming a control gate over at least a portion of the third dielectric layer.

16. A method for fabricating a semiconductor device, comprising:

forming a first dielectric layer over a substrate;

forming a gate electrode layer over the first dielectric layer;

forming a silicon oxynitride mask over the gate electrode layer;

etching the first dielectric layer and the gate electrode layer;

forming a bitline region in a portion of the substrate;

forming an oxide layer over the semiconductor device, the oxide layer filling regions etched by the etching;

polishing the oxide layer with a silica-based slurry for a first predetermined period of time at a first polishing rate;

polishing, at a second polishing rate that is faster than the first polishing rate, the oxide layer with a ceria-based slurry for a second predetermined period of time using the silicon oxynitride mask as a stop layer following the polishing the oxide layer with the silica-based slurry;

stripping the silicon oxynitride mask from the semiconductor device; and

forming a wordline conductor layer over the gate electrode layer and the oxide layer.

17. The method of claim 16 , where the silicon oxynitride layer has a thickness ranging from about 100 Å to about 500 Å.