Memory cell having combination raised source and drain and method of fabricating same
View Patent ↗A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.
1. A method of fabricating a memory device comprising:
providing a semiconductor substrate;
forming a charge trapping dielectric stack over the semiconductor substrate;
forming a gate electrode over the charge trapping dielectric stack; and
forming raised bitlines on opposite sides of the charge trapping dielectric stack and gate electrode, the step of forming raised bitlines including:
forming a lower portion of each bitline using a first forming process; and
forming an upper portion of each bitline using a second forming process;
wherein forming the lower portion of each bitline includes:
forming epitaxially grown silicon within a lower portion of each bitline opening; and
doping the epitaxially grown silicon in situ.
2. The method of claim 1 , further comprising:
patterning the charge trapping dielectric stack and the gate electrode; and
forming a pair of liners adjacent lateral sidewalls of the patterned charge trapping dielectric stack and gate electrode, adjacent liners defining a bitline opening.
3. The method of claim 2 , wherein the patterning includes forming shallow trenches within the substrate.
4. The method of claim 3 , wherein the shallow trenches have a depth of about 25 nanometers to about 100 nanometers.
5. The method of claim 1 , wherein the epitaxially grown silicon is doped in situ using phosphorous or arsenic.
6. The method of claim 1 , wherein forming the lower portion of each bitline includes:
forming the epitaxially grown silicon using a selective epitaxial growth (SEG) process.
7. The method of claim 6 , wherein forming the lower portion of each bitline further includes:
performing a hydrogen anneal process following the SEG process.
8. The method of claim 7 , wherein the hydrogen anneal process includes annealing the silicon formed by the SEG process in a hydrogen ambient at a temperature between about 750 degrees Celsius and 1,100 degrees Celsius, at a pressure of between about 10 Pascals (Pa) and 40 kiloPA for a time between about 5 seconds and about 60 minutes.
9. The method of claim 6 , further comprising:
before the step of forming epitaxially grown silicon, performing a bitline implant through each bitline opening.
10. The method of claim 9 , wherein at least one of the bitline implant and the forming of epitaxially grown silicon provides a diffusion region within the substrate.
11. The method of claim 6 , wherein forming the upper portion of each bitline includes:
filling the upper portion of the bitline opening with at least one of a metal, a metal-containing compound or n-doped polysilicon.
12. A memory device formed according to the method of claim 11 .
13. A memory device comprising:
a semiconductor substrate;
a charge trapping dielectric stack disposed over the semiconductor substrate;
a gate electrode disposed over the charge trapping dielectric stack, the gate electrode electrically defining a channel within a portion of the semiconductor substrate; and
a pair of raised bitlines, the bitlines having a lower portion that is formed by a first process and an upper portion that is formed by a second process;
wherein the lower portion of each bitline is comprised of in situ n-doped, epitaxially grown silicon.
14. The memory device of claim 13 , wherein the upper portion of each bitline has a vertical height that extends substantially adjacent a surface of the gate electrode.
15. The memory device of claim 14 , wherein the lower portion of each bitline is disposed at a vertical height that extends above an interface where the bottom of the charge trapping dielectric stack meets the semiconductor substrate.
16. The memory device of claim 15 , wherein a portion of the lower portion of each bitline is disposed within the semiconductor substrate.
17. The memory device of claim 16 , wherein the portion of the lower portion of the bitline disposed within the semiconductor substrate has a height of about 25 nanometers to about 100 nanometers.
18. The memory device of claim 13 , wherein the first process comprises:
forming in situ n-doped silicon using a selective epitaxial growth (SEG) process; and
annealing the in situ-doped silicon in a hydrogen ambient.
19. The memory device of claim 18 , wherein the upper portion of each bitline is comprised of at least one of a metal, a metal-containing compound or n-doped polysilicon.
20. The memory device of claim 19 , wherein the second process comprises:
filling a void above the lower portion of each bitline with at least one of a metal, a metal-containing compound or n-doped polysilicon.
21. The memory device of claim 19 , wherein each bitline includes a diffusion region within the semiconductor substrate.
22. The memory device of claim 21 , further comprising a pair of liners disposed laterally adjacent sidewalls of the charge trapping dielectric stack and the gate electrode, the liners having a thickness of about 10 nanometers to about 20 nanometers.
23. The memory device of claim 21 , wherein the upper and lower portions of each bitline have a lateral dimension of about 25 nanometers to about 50 nanometers.
24. The memory device of claim 23 , wherein the gate electrode electrically defines a channel within the substrate between adjacent diffusion regions, the channel having an effective length of about 80 nanometers to about 120 nanometers.
25. The memory device of claim 23 , wherein the gate electrode electrically defines a channel within the substrate between adjacent diffusion regions, the channel having a length, and the diffusion region of each bitline has a lateral dimension that is about 10% to about 20% of the length of the channel.
26. An array of the memory devices of claim 23 , wherein the pitch of the array of memory devices is about 180 nanometers, and the diffusion region of each bitline has a lateral dimension that is about 5% to about 10% of the pitch.
27. A method of forming bitlines for a semiconductor device, the method comprising:
patterning a plurality of layers formed over a semiconductor substrate, the patterning forming bitline openings within the layers;
forming a lower bitline portion within at least some of the bitline openings using a first forming process; and
forming an upper bitline portion over at least some of the lower bitline portions using a second forming process;
wherein the first forming process comprises:
forming in situ n-doped silicon using selective epitaxial growth (SEG) process; and
annealing the in situ n-doped silicon in a hydrogen ambient.
28. The method of claim 27 , wherein the first forming process provides doped silicon with minimal diffusion.
29. The method of claim 28 , wherein the second forming process provides a highly conductive material.
30. The method of claim 29 , wherein the second forming process comprises:
filling the remainder of at least some of the bitline openings with at least one of a metal, a metal-containing compound or n-doped polysilicon.