IP Library Granted Patent US 7,534,732
Granted Patent B1
US 7,534,732 · App. 11/356,311 · Granted May 19, 2009

Semiconductor devices with copper interconnects and composite silicon nitride capping layers

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Quick Facts
Patent No.
US 7,534,732
App. No.
11/356,311
Granted
May 19, 2009
Kind
B1
Abstract

Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

Claims (16)

1. A method of fabricating a semiconductor device, the method comprising:

depositing a layer of copper (Cu);

depositing a first silicon nitride layer having a first Si—H concentration, on the layer of Cu at a first SiH 4 flow rate of about 120 to about 180 sccm, and a first total RF power of about 640 watts to about 960 watts; and

depositing the second silicon nitride layer having a second Si—H concentration at a second SiH 4 flow rate of about 14 to about 24 sccm and the second total RF power of about 1,280 watts to about 1,920 watts.

2. The method according to claim 1 , comprising depositing the second silicon nitride layer at the second Si—H concentration of about 0.02% to about 0.06%.

3. The method according to claim 2 , comprising depositing the first silicon nitride layer at the first Si—H concentration of about 0.30% to about 0.90%.

4. The method according to claim 3 , comprising:

depositing the first silicon nitride layer at a first thickness; and

depositing the second silicon nitride layer at a second thickness greater than the first thickness.

5. The method according to claim 1 , wherein the semiconductor device includes a mirrorbit device comprising an oxide/nitride/oxide (ONO) gate dielectric stack on a substrate and a gate electrode on the gate dielectric stack.

6. The method according to claim 1 , comprising depositing the silicon nitride layer as one graded film by;

modifying the Si—H concentration throughout deposition; or

modifying the Si—H concentration at various discreet points during deposition.

7. The method according to claim 1 , wherein

said first silicon nitride layer is deposited by plasma enhanced chemical vapor deposition (PECVD) using ammonia and SiH 4 ; and

said second silicon nitride layer is deposited by PECVD using nitrogen and SiH 4 .

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2017
From: SPANSION LLC
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 042702/0460 →
RELEASE OF SECURITY INTEREST Recorded May 17, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 042486/0315 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2006
From: NGO, MINH VAN; WILSON, ERIK; PHAM, HIEU; HUERTAS, ROBERT; TOKUNO, HIROKAZU; YOU, LU; NICKEL, ALEXANDER; TRAN, MINH
To: SPANSION LLC; ADVANCED MICRO DEVICES, INC.
Reel/Frame 018304/0967 →