Granted Patent B2

US 8,815,727 · App. 13/644,387 · Granted Aug 26, 2014

Abstract

Claims (34)

1. A method for forming an integrated circuit comprising:

forming a semi-conducting layer over a substrate;

forming a spacer stack having a gap filler adjacent to the semi-conducting layer and an inter-layer dielectric over the gap filler, the gap filler comprising a different dielectric material than the inter-layer dielectric;

forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack; and

forming a metal layer in the recess.

2. The method as claimed in claim 1 wherein forming the semi-conducting layer of the substrate includes forming a charge trap layer over the substrate and below the semi-conducting layer.

3. The method as claimed in claim 1 further comprising planarizing the transition layer and the spacer stack.

4. The method as claimed in claim 1 wherein forming the transition layer adjacent to the spacer stack includes forming the transition layer adjacent to the inter-layer dielectric.

5. The method as claimed in claim 1 further comprising forming an electronic system or a subsystem with the integrated circuit.

6. A method for forming an integrated circuit comprising:

forming a polysilicon layer over a substrate;

forming a spacer stack having a nitride gap filler adjacent to the polysilicon layer and an oxide layer over the gap filler;

forming a tungsten nitride layer having a recess over the polysilicon layer and adjacent to the spacer stack; and

forming a tungsten layer in the recess.

7. The method as claimed in claim 6 wherein forming the polysilicon layer over the substrate includes:

forming a charge trap layer over the substrate and below the polysilicon layer; and

forming the nitride gap filler adjacent to the charge trap layer.

8. The method as claimed in claim 6 further comprising planarizing the tungsten layer, the tungsten nitride layer, and the spacer stack.

9. The method as claimed in claim 6 wherein forming the tungsten nitride layer having the recess over the polysilicon layer and adjacent to the spacer stack includes forming the tungsten nitride layer with a conformal configuration with the polysilicon layer and with an extension of the spacer stack.

10. The method as claimed in claim 6 further comprising forming a gate stack with the tungsten layer over the polysilicon layer.

11. A method for forming an integrated circuit, the method comprising:

forming a semi-conducting layer over a substrate;

forming a spacer stack having a gap filler and an inter-layer dielectric over the gap filler, the gap filler comprising a different dielectric material than the inter-layer dielectric;

forming a transition layer having a recess over the semi-conducting layer;

forming a metal layer in the recess.

12. The method of claim 11 wherein forming the semi-conducting layer includes forming a charge trap layer over the substrate and below the semi-conducting layer.

13. The method of claim 11 further comprising planarizing the transition layer.

14. The method of claim 11 further comprising planarizing the spacer stack.

15. The method of claim 11 wherein forming the transition layer is formed adjacent to the spacer stack.

16. The method of claim 15 wherein forming the transition layer adjacent to the spacer stack includes forming the transition layer adjacent to the inter-layer dielectric.

17. The method of claim 11 further comprising forming an electronic system with the integrated circuit.

18. The method of claim 11 wherein the semi-conducting layer is a polysilicon layer.

19. The method of claim 11 wherein the gap filler is a nitride gap filler.

20. The method of claim 11 wherein the metal layer in the recess comprises tungsten.

Assignments (7)