Method for decreasing sheet resistivity variations of an interconnect metal layer
View Patent ↗According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
1. A method comprising steps of:
forming a plurality of trenches in a dielectric layer situated over a wafer;
forming a metal layer over said dielectric layer and in said plurality of trenches such that said metal layer has a dome-shaped profile over said wafer;
performing a planarizing process to form a plurality of interconnect lines, each of said plurality of interconnect lines being situated in one of said plurality of trenches, said plurality of interconnect lines being situated in an interconnect metal layer;
wherein said dome-shaped profile of said metal layer causes said interconnect metal layer to have increased sheet resistivity uniformity across said wafer after said step of performing said planarizing process.
2. The method of claim 1 wherein said dome-shaped profile of said metal layer causes said dielectric layer to have a substantially planar top surface after said step of performing said planarizing process.
3. The method of claim 1 wherein said dome-shaped profile of said metal layer causes said plurality of interconnect lines to have a reduced thickness variation across said wafer.
4. The method of claim 1 wherein said metal layer has a first thickness over said dielectric layer over an approximate center of said wafer and a second thickness over said dielectric layer at an edge of said wafer, wherein said first thickness is greater than said second thickness.
5. The method of claim 4 wherein said first thickness is between 500.0 Angstroms and 3000.0 Angstroms greater than said second thickness.
6. The method of claim 1 wherein an apex of said metal layer is situated over an approximate center of said wafer.
7. The method of claim 1 wherein said planarizing process comprises a chemical mechanical polishing process.
8. The method of claim 1 wherein said metal layer comprises copper.
9. The method of claim 1 wherein said step of forming said metal layer comprises using a plating process to deposit said metal layer.
10. The method of claim 9 wherein said plating process uses a plurality of virtual concentric electrodes situated adjacent to said wafer, wherein a current flow in each of said plurality of virtual concentric electrodes is controlled to cause said metal layer to be deposited with said dome-shaped profile.
11. A method comprising steps of:
forming a plurality of trenches in a dielectric layer, said dielectric layer being situated over a wafer;
forming a metal layer over said dielectric layer and in said plurality of trenches such that said metal layer has a dome-shaped profile over said wafer;
performing a planarizing process to form a plurality of interconnect lines, wherein each of said plurality of interconnect lines are situated in one of said plurality of trenches, wherein said dome-shaped profile of said metal layer causes said plurality of interconnect lines to have a reduced thickness variation across said wafer.
12. The method of claim 11 wherein said dome-shaped profile of said metal layer causes said dielectric layer to have a substantially planar top surface after said step of performing said planarizing process.
13. The method of claim 11 wherein said plurality of interconnect lines are situated in an interconnect metal layer, wherein said dome-shaped profile of said metal layer causes said interconnect metal layer to have increased sheet resistivity uniformity across said wafer after said step of performing said planarizing process.
14. The method of claim 11 wherein said metal layer has a first thickness over said dielectric layer over an approximate center of said wafer and a second thickness over said dielectric layer at an edge of said wafer, wherein said first thickness is greater than said second thickness.
15. The method of claim 14 wherein said first thickness can be between 500.0 Angstroms and 3000.0 Angstroms greater than said second thickness.
16. The method of claim 11 wherein said planarizing process comprises a chemical mechanical polishing process.
17. The method of claim 11 wherein said step of forming said metal layer comprises using a plating process to deposit said metal layer.
18. The method of claim 17 wherein said plating process uses a plurality of virtual concentric electrodes situated adjacent to said wafer, wherein a current flow in each of said plurality of virtual concentric electrodes is controlled to cause said metal layer to be deposited with said dome-shaped profile.
19. The method of claim 11 wherein said metal layer comprises copper.