Cu annealing for improved data retention in flash memory devices
View Patent ↗Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N 2 atmosphere containing low H 2 or no H 2 , and at temperatures less than 200° C., e.g., 100° C. to 150° C.
1. A method of fabricating a semiconductor device, the method comprising:
depositing a layer of copper (Cu) or a Cu alloy in an opening in a dielectric layer, the opening being a dual damascene opening;
conducting chemical mechanical polishing (CMP) on an overburden formed in the depositing;
conducting a first anneal by heating the deposited layer of Cu or Cu alloy in an atmosphere of nitrogen (N 2 ) and 0 to 4 vol. % hydrogen (H 2 ), at a temperature of about 100° C. to less than 200° C. for up to 5 minutes; and, subsequently,
conducting a second anneal by heating the deposited layer of Cu or Cu alloy in N 2 without H 2 at a temperature of about 100° C. to less than 200° C., wherein both the first and second anneals are conducted after the CMP; and
wherein the semiconductor device comprises a mirrorbit device having a gate dielectric layer, comprising an oxide/nitride/oxide (ONO) stack on a substrate, and a gate electrode on the ONO stack.
2. The method according to claim 1 , wherein:
the dielectric layer has a dielectric constant (k) no greater than 3.9.
3. The method according to claim 1 , wherein the second anneal is conducted at a temperature no greater than that used in the first anneal.
4. The method according to claim 1 , wherein the first anneal is conducted in an atmosphere without H 2 .
5. The method according to claim 1 wherein at least one of the first anneal or the second anneal is conducted at a temperature from about 100° C. to about 150° C.
6. The method according to claim 1 , wherein:
the dielectric layer has a dielectric constant (k) equal to or less than 3.5.