Patent Assignment
Reel/Frame 047799/0036
Assignment of Assignor's Interest
Recorded: 2018-12-17
Pages: 4
Assignors
GUPTA, UMESH
Executed: 2018-12-13
KUMAR, NARESH
Executed: 2018-12-13
AGARWAL, RAKESH
Executed: 2018-12-13
KHANNA, SUKRITI
Executed: 2018-12-13
SHARMA, JAYANT
Executed: 2018-12-13
GOVILA, RITIKA
Executed: 2018-12-14
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Circuit Stage Credit Based Approaches to Static Timing Analysis of Integrated Circuits
Patent:
10,915,685 →
Application:
16/222,638 →