IP Library Assignment 051315/0035
Patent Assignment
Reel/Frame 051315/0035

Assignment of Assignor's Interest

Recorded: 2019-12-18 Pages: 3
Assignors
GARDNER, MARK I.
Executed: 2019-12-06
FULFORD, H. JIM
Executed: 2019-12-16
Assignee
TOKYO ELECTRON LIMITED
AKASAKA BIZ TOWER, 3-1 AKASAKA 5-CHOME, MINATO-KU, TOKYO, 107-6325, JAPAN
Covered Property (1)
Multiple Planes of Transistors with Different Transistor Architectures to Enhance 3D Logic and Memory Circuits
Application: 16/718,339 →
Publication: US 2021/0013326