Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits
Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V t (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.
1. A method of microfabrication, the method comprising:
receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other, in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel;
depositing a dielectric on the channels to a first predetermined thickness, wherein the dielectric is deposited all around a cross-section of the channels;
masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered;
removing the deposited dielectric from the second portion of the channels;
removing the first etch mask so that the channels are uncovered; and
depositing a high-k material on the channels, wherein the high-k material is deposited all around the cross-section of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels.
2. The method of claim 1 , wherein removing deposited dielectric includes removing a second predetermined thickness of the deposited dielectric resulting in the first portion of the channels having the first predetermined thickness of dielectric and the second portion of the channels having a third predetermined thickness of dielectric, the first predetermined thickness of dielectric being greater than the third predetermined thickness of dielectric.
3. The method of claim 1 , further comprising depositing an interfacial layer of dielectric all around a cross-section of the channels subsequent to removing the first etch mask and prior to depositing the high-k material.
4. The method of claim 1 , further comprising selecting the high-k material from the group including HfO 2 , Al 2 O 3 , Y 2 O 3 and ZrO 2 .
5. The method of claim 1 , further comprising depositing work function metal layers subsequent to depositing the high-k material, wherein the work function metal layers include a first work function metal layer of titanium nitride, TiN, and a second work function metal layer of tantalum nitride, TaN, wherein the TaN layer is deposited over the TiN layer.
6. The method of claim 5 , further comprising depositing a third work function metal layer of titanium oxy nitride, TiON, over the TaN layer.
7. The method of claim 5 , further comprising depositing a third work function metal layer of titanium carbide, TiC, over the TaN layer.
8. The method of claim 5 , further comprising depositing a third work function metal layer of titanium aluminum, TiAl, over the TaN layer.
9. The method of claim 5 , further comprising depositing the dielectric, the high-k material and work function metals by one or more deposition methods selected from the group of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion and low pressure CVD.