IP Library › Assignment 051376/0752
Patent Assignment
Reel/Frame 051376/0752

Assignment of Assignor's Interest

Recorded: 2019-12-27 Pages: 3
Assignors
WU, CHENG-HSIEN
Executed: 2017-07-27
CHEN, I-SHENG
Executed: 2017-07-27
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property (1)
Lattice-Mismatched Semiconductor Substrates with Defect Reduction
Application: 16/728,393 →
Publication: US 2020/0144050