Lattice-mismatched semiconductor substrates with defect reduction
A structure includes a substrate having a first semiconductor material. The substrate has a recess. A bottom portion of the recess has a first sidewall and a second sidewall. The first sidewall intersects the second sidewall. The structure further includes an isolation feature surrounding the recess and a second semiconductor material disposed in the recess and in contact with the first semiconductor material. The second semiconductor material has lattice mismatch to the first semiconductor material.
1. A structure, comprising:
a substrate including a first semiconductor material, the substrate having a recess, a bottom portion of the recess having a first sidewall and a second sidewall, the first sidewall intersecting the second sidewall at a position below a top surface of the substrate;
an isolation feature surrounding the recess, wherein topmost portions of the first and second sidewalls intersect sidewalls of the isolation feature, and wherein a bottommost portion of the isolation feature extends downward below the top surface of the substrate; and
a second semiconductor material disposed in the recess and in contact with the first semiconductor material, the second semiconductor material having lattice mismatch to the first semiconductor material.
2. The structure of claim 1 , wherein dislocations in the second semiconductor material due to the lattice mismatch propagate from the first sidewall to the second sidewall in a direction parallel to the top surface of the substrate.
3. The structure of claim 2 , wherein the first semiconductor material includes ( 001 ) silicon and the direction is a < 110 > crystallographic direction defined by the ( 001 ) silicon.
4. The structure of claim 3 , wherein the first sidewall comprises a ( 111 ) crystallographic plane defined by the ( 001 ) silicon.
5. The structure of claim 1 , wherein the first sidewall and the second sidewall intersect at a vertex, thereby defining a V-shape groove between the first sidewall and the second sidewall, the V-shape groove having a top opening that has a width, the vertex having a distance to the top opening, the width being at least √{square root over (2)} times the distance.
6. The structure of claim 1 , wherein the first sidewall defines an angle with respect to the top surface of the substrate and the angle is in a range from 45° to 59°.
7. The structure of claim 1 , wherein the bottommost portion of the isolation feature is lower than a topmost portion of the first sidewall.
8. A structure, comprising:
a substrate having a trench, wherein a top portion of the trench has dielectric sidewalls, a bottom portion of the trench has semiconductor sidewalls comprising a first semiconductor material, and at least one of the semiconductor sidewalls is not perpendicular to a top surface of the substrate;
a second semiconductor material disposed in the trench and in contact with the semiconductor sidewalls, wherein the second semiconductor material is different from the first semiconductor material; and
multiple fins of the second semiconductor material in the trench.
9. The structure of claim 8 , further comprising a dielectric material between the multiple fins.
10. The structure of claim 9 , wherein the dielectric sidewalls include a second dielectric material that is different from the dielectric material between the multiple fins.
11. The structure of claim 8 , wherein the at least one of the semiconductor sidewalls forms an angle in a range from 45° to 59° to the top surface of the substrate.
12. The structure of claim 8 , wherein dislocations in the second semiconductor material due to lattice mismatch propagate in a direction parallel to the top surface of the substrate.
13. The structure of claim 8 , wherein a width of the trench is at least 50 nm.
14. The structure of claim 8 , wherein at least one of the dielectric sidewalls is not perpendicular to the top surface of the substrate.
15. A structure, comprising:
a substrate having a recess, wherein sidewalls of a lower portion of the recess include a first semiconductor material, and sidewalls of an upper portion of the recess include a first dielectric material;
a second semiconductor material disposed in the recess, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material providing multiple fins; and
an isolation feature between the multiple fins.
16. The structure of claim 15 , wherein the isolation feature comprises a different dielectric material than the first dielectric material.
17. The structure of claim 15 , wherein at least one of the sidewalls of the lower portion of the recess forms an angle with respect to a top surface of the substrate, and the angle is in a range from 45° to 59°.
18. The structure of claim 15 , wherein the first semiconductor material includes ( 001 ) silicon and one of the sidewalls of the lower portion of the recess comprises a ( 111 ) crystallographic plane defined by the ( 001 ) silicon.
19. The structure of claim 15 , wherein dislocations in the second semiconductor material due to lattice mismatch with the first semiconductor material propagate in a direction parallel to a top surface of the substrate.
20. The structure of claim 1 , wherein in a cross-sectional plane perpendicular to a lengthwise direction of the recess, topmost portions of the first and second sidewalls have a lateral distance and the first sidewall has a length, the length is less than about √{square root over ( 3 )}/ 2 times the lateral distance.