Patent Assignment
Reel/Frame 054107/0323
Assignment of Assignor's Interest
Recorded: 2020-10-20
Pages: 4
Assignors
CHUANG, YI-LIN
Executed: 2020-10-07
TAN, SHI-WEN
Executed: 2020-10-07
LIU, SONG
Executed: 2020-10-07
LIN, SHIH-YAO
Executed: 2020-10-07
FANG, WEN-YUAN
Executed: 2020-10-07
Assignees
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
TSMC NANJING COMPANY LIMITED
16, ZIFENG ROAD, PUKOU ECONOMIC DEVELOPMENT ZONE, NANJING, JIANGSU PROVINCE, CHINA
Covered Property
(1)
Method for Optimizing Floor Plan for an Integrated Circuit