Method for optimizing floor plan for an integrated circuit

1. A method, comprising:

generating a floor plan having a plurality of macros for an integrated circuit;

adjusting the plurality of macros according to a channel area interposed between a plurality of pins;

separating the plurality of macros by a channel width of the channel area; and

adjusting, in accordance with correlations between the plurality of macros and a plurality of registers, the plurality of macros in the floor plan.

2. The method of claim 1 , further comprising:

organizing the plurality of macros into a plurality of first group boxes extending in a first direction and a plurality of second group boxes extending in a second direction; and

aligning macros in the plurality of first group boxes according to a minimum total movements of the macros in the plurality of first group boxes.

3. The method of claim 2 , further comprising:

moving the macros in the plurality of second group boxes, wherein movements of the macros range between a first space and a second space,

wherein the first space corresponds to a space between one of the macros and a left boundary of each the plurality of second group boxes or another one of the macros, and

the second space corresponds to a space between one of the macros and a right boundary of each the plurality of second group boxes or another one of the macros.

4. The method of claim 1 , wherein adjusting the plurality of macros comprises:

generating a chain map of the plurality of macros; and

in response to searching the chain map, flipping corresponding macros in the plurality of macros to change orientations of the plurality of pins of the corresponding macros, wherein a pin of one of the plurality of macros and a pin of one of the corresponding macros in the plurality of macros face each other.

5. The method of claim 1 , wherein when a number of the plurality of macros is an odd number and a first macro of the plurality of macros is adjacent a boundary of the floor plan, an orientation of a pin of the first macro is arranged opposite of the boundary of the floor plan.

6. The method of claim 1 , further comprising:

partitioning a plurality of standard cells;

estimating a number of a plurality of buffers according to a predicted channel path for each of the plurality of macros, wherein the predicted channel path is between one of the plurality of standard cells and a corresponding one of the plurality of macros;

on the basis of the number of the plurality of buffers and an area of each of the plurality of buffers, calculating a predicted channel width for the corresponding one of the plurality of macros; and

determining the channel width according to the predicted channel widths of the plurality of macros.

7. The method of claim 6 , further comprising:

determining a start point on the corresponding one of the plurality of macros and a corresponding end point on the plurality of standard cells; and

generating the predicted channel path extending from the start point on the corresponding one of the plurality of macros to the corresponding end point on the plurality of standard cells,

wherein the predicted channel path has a shortest distance between the start point on the corresponding one of the plurality of macros and the corresponding end point on the plurality of standard cells.

8. The method of claim 1 , wherein adjusting the plurality of macros in the floor plan comprises:

detecting correlations between the plurality of macros and the plurality of registers; and

in response to detecting, generating a sequence of the plurality of macros corresponding to one of the plurality of registers.

9. The method of claim 1 , further comprising:

on the basis of a comparison of a plurality of weights of the plurality of macros, placing the plurality of macros in the floor plan, wherein a weight of one of the plurality of macros corresponds to a connection relationship of the one of the plurality of macros.

10. The method of claim 9 , wherein the connection relationship of the one of the plurality of macros is associated with a number of a plurality of fan-in points, a number of a plurality of fan-out points, and a number of stages between the one of the plurality of macros and the plurality of registers coupled thereto.

11. The method of claim 1 , further comprising:

placing a centroid of a first portion of the plurality of macros a distance away from a closest boundary in the floor plan, wherein each macro of the first portion of the plurality of macros is at a spacing from a second portion of the plurality of macros;

wherein the distance is greater than about 50 micrometers, and the spacing is greater than about 2 micrometers.

12. A system, comprising:

one or more processing units; and

a memory unit configured to store instructions that when executed by at least one of the one or more processing units perform operations, comprising:

place a plurality of macros around a centroid of a region in a floor plan according to a plurality of weights of the plurality of macros;

adjust a plurality of pins of the plurality of macros to face each other;

predict a channel width for each of a plurality of channels interposed between the plurality of macros;

adjust the plurality of macros according to the channel width of each of the plurality of channels;

detect correlations between the plurality of macros and a plurality of registers; and

adjust the plurality of macros according to the correlations.

13. The system of claim 12 , wherein the operations further comprise:

define a plurality of group boxes for the plurality of macros; and

align the plurality of macros with a plurality of boundaries of the plurality of group boxes.

14. The system of claim 12 , wherein the operations further comprise:

compare the plurality of weights of the plurality of macros, wherein each of the plurality of weights is associated with a number of a plurality of fan-in points, a number of a plurality of fan-out points, and a number of stages between the one of the plurality of macros and the plurality of registers coupled thereto.

15. The system of claim 12 , wherein the operations further comprise:

sort the plurality of macros according to the correlations; and

generate a sequence of the plurality of macros in response to sorting.

16. The system of claim 12 , wherein the operations further comprise:

detect a power switch cell in the floor plan; and

adjust the channel width in response to detecting.

17. A method, comprising:

placing, in accordance with a plurality of weights of a plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region in a floor plan of an integrated circuit than a second portion of the plurality of macros; and

separating the plurality of macros by a plurality of channels, wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros.

18. The method of claim 17 , wherein the plurality of weights of the first portion of the plurality of macros are greater than the plurality of weights of the second portion of the plurality of macros.

19. The method of claim 17 , further comprising:

arranging a plurality of standard cells adjacent to the plurality of macros;

wherein each of the plurality of channels has a channel width, and the channel width is associated with a shortest channel path between one of the plurality of standard cells and one of the plurality of macros.

20. The method of claim 17 , further comprising:

adjusting, according to correlations between the plurality of macros and a plurality of registers, a third portion of the plurality of macros to be closer to a first register of the plurality of registers and a fourth portion of the plurality of macros to be closer to a second register, different from the first register, of the plurality of registers.