Patent Assignment
Reel/Frame 059418/0163
Assignment of Assignor's Interest
Recorded: 2022-03-28
Pages: 5
Assignors
HSU, CHUNG-WEI
Executed: 2022-02-21
CHIANG, KUO-CHENG
Executed: 2022-02-21
HUANG, MAO-LIN
Executed: 2022-02-21
CHU, LUNG-KUN
Executed: 2022-02-22
YU, JIA-NI
Executed: 2022-02-21
LU, CHUN-FU
Executed: 2022-02-22
WANG, CHIH-HAO
Executed: 2022-02-21
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property
(1)
Method of Forming a Transistor Device Having Dipole-Containing Gate Dielectric Layer and Fluorine-Containing Gate Dielectric Layer