IP Library › Granted Patent US 12,288,695
Granted Patent B2
US 12,288,695 · App. 17/705,004 · Granted Apr 29, 2025

Method of forming a transistor device having dipole-containing gate dielectric layer and fluorine-containing gate dielectric layer

Inventors: Chung-Wei Hsu (Baoshan Township, TW); Kuo-Cheng Chiang (Zhubei, TW); Mao-Lin Huang (Hsinchu, TW); Lung-Kun Chu (New Taipei, TW); Jia-Ni Yu (New Taipei, TW); Chun-Fu Lu (Hsinchu, TW); Chih-Hao Wang (Baoshan Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/324H01L21/823412H01L29/0665H01L29/42392H01L29/66742H01L29/78618H01L29/78696
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Quick Facts
Patent No.
US 12,288,695
App. No.
17/705,004
Granted
Apr 29, 2025
Kind
B2
Abstract

A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Claims (62)

1. A method of forming a semiconductor device, wherein the method comprises:

forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region;

introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region, wherein introducing the first dipole element into the first dielectric layer comprises:

forming a first dipole layer over the first dielectric layer in the first region and in the second region, wherein the first dipole layer comprises an oxide of the first dipole element;

removing a portion of the first dipole layer in the second region;

applying a thermal treatment to the first dipole layer; and

after applying the thermal treatment to the first dipole layer, removing remaining portions of the first dipole layer over the first channel region;

after introducing the first dipole element, forming a second dielectric layer over the first dipole-containing gate dielectric layer;

introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and

forming a gate electrode over the first fluorine-containing gate dielectric layer.

2. The method of claim 1 , wherein introducing fluorine comprises:

exposing the second dielectric layer to a fluorine-containing gaseous environment; and

annealing to diffuse fluorine from the fluorine-containing gaseous environment into the second dielectric layer.

3. The method of claim 1 , wherein introducing fluorine comprises:

forming a fluorine-containing layer over the second dielectric layer; and

annealing to diffuse fluorine from the fluorine-containing layer into the second dielectric layer.

4. The method of claim 1 , further comprising after forming the first dipole-containing gate dielectric layer in the first region, introducing a second dipole element to the first dielectric layer in the second region to form a second dipole-containing gate dielectric layer in the second region.

5. The method of claim 4 , wherein introducing the second dipole element into the first dielectric layer comprises:

forming a second dipole layer over the first dielectric layer in the second region and the first dipole-containing gate dielectric layer in the first region, wherein the second dipole layer comprises an oxide of the second dipole element;

applying a thermal treatment to the second dipole layer; and

after applying the thermal treatment to the second dipole layer, removing remaining portions of the second dipole layer in the second region before forming the second dielectric layer,

wherein forming the second dielectric layer over the first dipole-containing gate dielectric layer comprises forming the second dielectric layer over the first dipole-containing gate dielectric layer in the first region and over the second dipole-containing gate dielectric layer in the second region.

6. The method of claim 5 , further comprising removing a portion of the second dipole layer in the first region before applying the thermal treatment to the second dipole layer.

7. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer are formed of a same material.

8. A method comprising:

depositing a first gate dielectric layer over a first semiconductor structure in a first device region and over a second semiconductor structure in a second device region;

depositing a first dipole layer over the first gate dielectric layer;

selectively removing the first dipole layer from over the first gate dielectric layer in the second device region;

after selectively removing the first dipole layer from over the first gate dielectric layer in the second device region, diffusing a first dipole element of the first dipole layer into the first gate dielectric layer in the first device region to form a first doped gate dielectric layer;

removing the first dipole layer from over the first doped gate dielectric layer in the first device region;

depositing a second dipole layer over the first gate dielectric layer in the second device region;

diffusing a second dipole element of the second dipole layer into the first gate dielectric layer in the second device region;

forming a second gate dielectric layer over the first doped gate dielectric layer, wherein a peak concentration of fluorine of the second gate dielectric layer is greater than a peak concentration of fluorine of the first gate dielectric layer, wherein forming the second gate dielectric layer comprises:

depositing the second gate dielectric layer over the first doped gate dielectric layer after removing the first dipole layer from over the first gate dielectric layer in the first device region; and

diffusing fluorine into the second gate dielectric layer; and

forming a gate electrode over the second gate dielectric layer.

9. The method of claim 8 , wherein diffusing fluorine into the second gate dielectric layer comprises soaking the second gate dielectric layer in a gaseous environment, the gaseous environment comprising fluorine.

10. The method of claim 8 , diffusing fluorine into the second gate dielectric layer comprises:

depositing a fluorine-containing layer over the second gate dielectric layer; and

diffusing fluorine from the fluorine-containing layer into the second gate dielectric layer.

11. The method of claim 8 further comprising:

depositing a barrier layer over the second gate dielectric layer prior to diffusing fluorine into the second gate dielectric layer; and

removing the barrier layer after diffusing fluorine into the second gate dielectric layer, wherein diffusing fluorine into the second gate dielectric layer comprises diffusing fluorine into the second gate dielectric layer through the barrier layer.

12. The method of claim 8 , wherein the first dipole element and the second dipole element are concurrently diffused into the first gate dielectric layer.

13. The method of claim 8 , wherein the first dipole element has a same conductivity type as the second dipole element.

14. The method of claim 8 , wherein the first dipole element has an opposite conductivity type as the second dipole element.

15. A method comprising:

forming an interfacial layer over a channel region;

forming a gate dielectric over the interfacial layer, wherein forming the gate dielectric comprises:

forming a first gate dielectric material over the channel region, wherein the first gate dielectric material comprises a dipole element;

forming a second gate dielectric material over the first gate dielectric material; and

diffusing fluorine into at least the second gate dielectric material, wherein a peak concentration of fluorine in the gate dielectric is in the second gate dielectric material; and

forming a gate electrode over the gate dielectric.

16. The method of claim 15 , wherein the second gate dielectric material is thicker than the first gate dielectric material.

17. The method of claim 15 , wherein forming the gate dielectric further comprises diffusing fluorine into the first gate dielectric material.

18. The method of claim 15 , wherein forming the first gate dielectric material comprises:

forming a first dielectric layer;

forming a first dipole layer over the first dielectric layer, wherein the first dipole layer comprises an oxide of the dipole element;

applying a thermal treatment to the first dipole layer; and

after applying the thermal treatment to the first dipole layer, removing remaining portions of the first dipole layer.

19. The method of claim 15 , wherein a peak concentration of first dipole element is in the first gate dielectric material.

20. The method of claim 15 , wherein over 60% of the fluorine is distributed in the second gate dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2022
From: HSU, CHUNG-WEI; CHIANG, KUO-CHENG; HUANG, MAO-LIN; CHU, LUNG-KUN; YU, JIA-NI; LU, CHUN-FU; WANG, CHIH-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 059418/0163 →
Continuity (2)
Provisional Application 63256172 · Oct 15, 2021
Related Publication 20230120117A1 · Apr 20, 2023
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