IP Library › Granted Patent US 11,610,822
Granted Patent B2
US 11,610,822 · App. 16/925,893 · Granted Mar 21, 2023

Structures for tuning threshold voltage

Inventors: Yen-Yu Chen (Taichung, TW); Chung-Liang Cheng (Changhua County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/823857H01L21/0337H01L21/823821H01L21/823828H01L27/0922H01L29/0673H01L29/4966H01L29/7851
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,610,822
App. No.
16/925,893
Granted
Mar 21, 2023
Kind
B2
Abstract

A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

Claims (49)

1. A device, comprising:

a substrate;

an interfacial layer formed over the substrate, wherein the interfacial layer has a dipole-penetrated portion;

a gate dielectric layer formed over the interfacial layer, wherein the gate dielectric layer has a dipole-diffused portion, and wherein a concentration of a dipole material at a bottom of the gate dielectric layer is greater than a rest of the gate dielectric layer; and

a metal gate electrode formed over the gate dielectric layer, wherein the metal gate electrode includes, a first protective layer, a second protective layer, a work function metal layer disposed between the first protective layer and the second protective layer such that a bottom surface of the work function metal layer is in direct contact with an upper surface of the first protective layer, and a dielectric capping layer disposed over the second protective layer, wherein a bottom surface of the dielectric capping layer is in direct contact with an upper surface of the second protective layer, wherein the work function metal layer has a different material composition than the first protective layer and the second protective layer, and wherein the first protective layer and the second protective layer have a same material composition.

2. The device of claim 1 , wherein a concentration of a dipole material within the dipole-penetrated portion decreases as a distance from an upper surface of the dipole-penetrated portion increases.

3. The device of claim 1 , wherein the dipole-penetrated portion and the dipole-diffused portion contain yttrium oxide, magnesium oxide, niobium oxide, titanium oxide, boron oxide, phosphorous pentoxide, or phosphorous trioxide.

4. The device of claim 1 , wherein:

the metal gate electrode further includes a glue layer disposed over the dielectric capping layer, and a fill metal component disposed over the glue layer.

5. The device of claim 4 , wherein the work function metal layer includes TiAlC, wherein the first protective layer and the second protective layer each include TiN, wherein the dielectric capping layer includes SiO 2 , wherein the glue layer includes TiN or TaN, and wherein the fill metal component includes W, Co, Ru, or Ir.

6. The device of claim 1 , wherein the device includes a FinFET device or a gate-all-around device, and wherein an oxygen content in the work function metal layer is less than about 1%.

7. A device, comprising:

a substrate;

an interfacial layer located over the substrate, wherein the interfacial layer contains a dipole material;

a gate dielectric layer located over the interfacial layer, wherein the gate dielectric layer contains the dipole material, and wherein a concentration of the dipole material at a bottom of the gate dielectric layer is greater than a rest of the gate dielectric layer; and

a metal-containing gate electrode located over the gate dielectric layer, wherein the metal gate electrode includes a work function metal layer disposed between a first protective layer and a second protective layer such that a bottom surface of the work function metal layer is in direct contact with an upper surface of the first protective layer, wherein the metal gate electrode further includes a dielectric capping layer disposed over the second protective layer, a glue layer disposed over the dielectric capping layer, and a fill metal layer disposed over the glue layer, wherein the work function metal layer has a different material composition than the first protective layer and the second protective layer, and wherein the first protective layer and the second protective layer have a same material composition.

8. The device of claim 7 , wherein a concentration of the dipole material varies based on a depth within the interfacial layer.

9. The device of claim 7 , wherein the dipole material contains yttrium oxide, magnesium oxide, niobium oxide, titanium oxide, boron oxide, phosphorous pentoxide, or phosphorous trioxide.

10. The device of claim 7 , wherein:

a bottom surface of the dielectric capping layer is in physical contact with an upper surface of the second protective layer, and a bottom surface of the glue layer is in physical contact with an upper surface of the dielectric capping layer.

11. The device of claim 10 , wherein an oxygen content in the work function metal layer is less than about 1%.

12. The device of claim 11 , wherein:

the work function metal layer contains TiAlC;

the first protective layer and the second protective layer each contain TiN;

the dielectric capping layer includes SiO 2 ;

the glue layer includes TiN or TaN; and

the fill metal layer includes W, Co, Ru, or Ir.

13. The device of claim 7 , wherein the device is a gate-all-around (GAA) device.

14. A device, comprising:

a substrate;

an interfacial layer located over the substrate, wherein the interfacial layer contains a dipole material;

a gate dielectric layer located over the interfacial layer, wherein the gate dielectric layer contains the dipole material; and

a metal-containing gate electrode located over the gate dielectric layer;

wherein:

a concentration of the dipole material varies within the interfacial layer and the gate dielectric layer;

a peak concentration of the dipole material within the interfacial layer occurs proximate to an interface between the interfacial layer and the gate dielectric layer; and

a peak concentration of the dipole material within the gate dielectric layer occurs at a bottom of the gate dielectric layer;

the metal gate electrode includes a first protective layer, a second protective layer, a work function metal layer disposed between the first protective layer and the second protective layer, and a dielectric capping layer disposed over the second protective layer;

a bottom surface of the dielectric capping layer is in direct contact with an upper surface of the second protective layer;

a bottom surface of the work function metal layer is in direct contact with an upper surface of the first protective layer;

the work function metal layer has a different material composition than the first protective layer and the second protective layer;

the first protective layer and the second protective layer have a same material composition; and

an oxygen content in the work function metal layer is less than about 1%.

15. The device of claim 14 , wherein a lowest concentration of the dipole material within the interfacial layer occurs at a point farthest away from the interface between the interfacial layer and the gate dielectric layer.

16. The device of claim 14 , wherein the dipole material includes yttrium oxide, magnesium oxide.

17. The device of claim 14 , wherein the dipole material includes niobium oxide, titanium oxide, boron oxide, phosphorous pentoxide, or phosphorous trioxide.

18. The device of claim 14 , wherein the interfacial layer is a first interfacial layer of a first gate, the dipole material is a first dipole material, the gate dielectric layer is a first gate dielectric layer of the first gate, and the metal-containing gate electrode is a first metal-containing gate electrode of the first gate, and wherein the device further comprises a second gate that includes a second interfacial layer that contains a second dipole material, a second gate dielectric layer located over the second interfacial layer, and a second metal-containing gate electrode located over the second gate dielectric layer, and wherein the concentration of the first dipole material in the first interfacial layer is different than a concentration of the second dipole material in the second interfacial layer.

19. The device of claim 18 , wherein the first gate and the second gate are associated with different threshold voltages.

20. The device of claim 18 , wherein the first dipole material and the second dipole material are both N-type dipole materials or are both P-type dipole materials.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2020
From: CHEN, YEN-YU; CHENG, CHUNG-LIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053175/0452 →
Continuity (2)
Provisional Application 62968482 · Jan 31, 2020
Related Publication 20210242092A1 · Aug 5, 2021
Cited By (1)
US 12,288,695