Patent Assignment
Reel/Frame 060211/0752
Assignment of Assignor's Interest
Recorded: 2022-06-15
Pages: 8
Assignors
SUTHERLAND, JEANNETTE NEWMAN
Executed: 2022-06-08
DHURIA, AMIT
Executed: 2022-06-13
VEERAVALLI, ARVIND NEMBILI
Executed: 2022-06-15
KIRIHENNEDIGE, SARATH JAYALATH
Executed: 2022-06-15
KERSULIS, SAULIUS
Executed: 2022-06-15
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System and Method for Comparing Circuit Design Constraint Sets
Patent:
12,475,286 →
Application:
17/841,056 →