System and method for comparing circuit design constraint sets
Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set. The embodiments may further include creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set. The embodiments may also include determining, using the at least one processor, at least one of: a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and an equivalent path exception corresponding to the at least one endpoint.
1 . A computer-implemented method for comparing constraint sets of a circuit design, comprising:
determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set of the circuit design;
creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set;
determining, using the at least one processor, at least one of:
a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and
an equivalent path exception corresponding to the at least one endpoint and based at least in part on the arrival propagation time, the first tag, and the second tag, wherein determining at least one of a non-equivalent path and an equivalent path includes comparing all constraints of the first constraint set with all constraints of the second constraint set; and
indicating, using the at least one processor, at least one of the non-equivalent path exception and the equivalent path exception.
2 . The computer-implemented method of claim 1 , further comprising:
creating at least one timing graph based at least in part on at least one of the first constraint set and the second constraint set.
3 . The computer-implemented method of claim 1 , further comprising:
mapping, based upon at least in part one or more clock characteristics and one or more definition points in the circuit design, a first clock associated with the first constraint set to a second clock associated with the second constraint set, wherein mapping includes determining an equivalence between the first clock and the second clock.
4 . The computer-implemented method of claim 2 , further comprising:
propagating the first tag associated with the first constraint set and the second tag associated with the second constraint set through the at least one timing graph.
5 . The computer-implemented method of claim 2 , wherein at least one of the first tag and the second tag are embedded in timing data propagated through the at least one timing graph.
6 . The computer-implemented method of claim 2 , wherein the comparing of the constraint sets of the circuit design is performed at the at least one timing endpoint during propagation of the at least one timing graph and is based on, at least in part, the first tag and the second tag.
7 . The computer-implemented method of claim 1 , wherein the first tag corresponds to a first phase of a first view associated with the first constraint set, the second tag corresponds to a second phase of a second view associated with the second constraint set, the first view includes the second tag, and the second view includes the first tag.
8 . A non-transitory computer-readable storage medium having stored thereon instructions that when executed by a machine result in the following operations:
determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set of a circuit design;
creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set;
determining, using the at least one processor, at least one of:
a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and
an equivalent path exception corresponding to the at least one endpoint and based at least in part on the arrival propagation time, the first tag, and the second tag; and
indicating, using the at least one processor, at least one of the non-equivalent path exception and the equivalent path exception, wherein determining at least one of a non-equivalent path and an equivalent path includes comparing all constraints of the first constraint set with all constraints of the second constraint set.
9 . The non-transitory computer-readable storage medium of claim 8 , further comprising:
creating at least one timing graph based at least in part on at least one of the first constraint set and the second constraint set.
10 . The non-transitory computer-readable storage medium of claim 8 , further comprising:
mapping, based upon at least in part one or more clock characteristics and one or more definition points in the circuit design, a first clock associated with the first constraint set to a second clock associated with the second constraint set, wherein mapping includes determining an equivalence between the first clock and the second clock.
11 . The non-transitory computer-readable storage medium of claim 9 , further comprising:
propagating the first tag associated with the first constraint set and the second tag associated with the second constraint set through the at least one timing graph.
12 . The non-transitory computer-readable storage medium of claim 9 , wherein at least one of the first tag and the second tag are embedded in timing data propagated through the at least one timing graph.
13 . The non-transitory computer-readable storage medium of claim 9 , wherein the comparing of the constraint sets of the circuit design is performed at the at least one timing endpoint during propagation of the at least one timing graph and is based on, at least in part, the first tag and the second tag.
14 . The non-transitory computer-readable storage medium of claim 9 , wherein the first tag corresponds to a first phase of a first view associated with the first constraint set, the second tag corresponds to a second phase of a second view associated with the second constraint set, the first view includes the second tag, and the second view includes the first tag.
15 . A system comprising a computing device having at least one processor and a memory, wherein the at least one processor is configured to:
determine at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set of a circuit design;
create a first tag associated with the first constraint set and a second tag associated with the second constraint set;
determine at least one of:
a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and
an equivalent path exception corresponding to the at least one endpoint and based at least in part on the arrival propagation time, the first tag, and the second tag; and
indicate at least one of the non-equivalent path exception and the equivalent path exception, wherein determining at least one of a non-equivalent path and an equivalent path includes comparing all constraints of the first constraint set with all constraints of the second constraint set.
16 . The system of claim 15 , wherein the at least one processor is further configured to:
create at least one timing graph based at least in part on at least one of the first constraint set and the second constraint set.
17 . The system of claim 15 , wherein the at least one processor is further configured to:
map, based upon at least in part one or more clock characteristics and one or more definition points in the circuit design, a first clock associated with the first constraint set to a second clock associated with the second constraint set, wherein mapping includes determining an equivalence between the first clock and the second clock.
18 . The system of claim 16 , wherein the at least one processor is further configured to:
propagate the first tag associated with the first constraint set and the second tag associated with the second constraint set through the at least one timing graph.
19 . The system of claim 16 , wherein at least one of the first tag and the second tag are embedded in timing data propagated through the at least one timing graph.
20 . The system of claim 15 , wherein the first tag corresponds to a first phase of a first view associated with the first constraint set, the second tag corresponds to a second phase of a second view associated with the second constraint set, the first view includes the second tag, and the second view includes the first tag.